LIGHT EMITTING DIODE DRIVING CIRCUIT AND LIGHT EMITTING DIODE ARRAY DEVICE
    21.
    发明申请
    LIGHT EMITTING DIODE DRIVING CIRCUIT AND LIGHT EMITTING DIODE ARRAY DEVICE 有权
    发光二极管驱动电路和发光二极管阵列器件

    公开(公告)号:US20110298382A1

    公开(公告)日:2011-12-08

    申请号:US13209122

    申请日:2011-08-12

    Abstract: There is provided an LED driving circuit including: at least one ladder network circuit including: (n+1) number of first branches connected in parallel with one another by n number of first middle junction points between a first junction point and a second junction point, where n denotes an integer satisfying n≧2, (n+1) number of second branches connected in parallel with one another by n number of second middle junction points between the first junction point and the second junction point, the (n+1) number of second branches connected in parallel with the first branches; and n number of middle branches connecting the first and second middle junction points of an identical m sequence to each other, respectively, wherein each of the first and second, and middle branches comprises at least one LED device.

    Abstract translation: 提供了一种LED驱动电路,包括:至少一个梯形网络电路,包括:(n + 1)数个第一分支,其在第一连接点和第二连接点之间彼此并联连接n个第一中间连接点 ,其中n表示满足n≥2的整数,(n + 1)个在第一连接点和第二连接点之间由n个第二中间连接点彼此并联连接的第二分支数,第(n + 1)个 )与第一分支并联连接的第二分支的数量; 以及分别将相同m个序列的第一和第二中间连接点彼此连接的n个中间分支,其中第一和第二和中间分支中的每一个包括至少一个LED装置。

    METAL LINE OF SEMICONDUCTOR DEVICE WITH A TRIPLE LAYER DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME
    25.
    发明申请
    METAL LINE OF SEMICONDUCTOR DEVICE WITH A TRIPLE LAYER DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME 审中-公开
    具有三层扩散障碍物的半导体器件的金属线及其形成方法

    公开(公告)号:US20090001577A1

    公开(公告)日:2009-01-01

    申请号:US11939054

    申请日:2007-11-13

    Abstract: A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region and a metal line is formed to fill the metal line forming region of the insulation layer. The diffusion barrier is formed between the metal line and the insulation layer. The diffusion barrier has a structure in which a TaSixNy layer is interposed between a first Ta-based layer and a second Ta-based layer. A metal line formed in this manner prevents the contact resistance of the metal line from increasing and the leakage current characteristics from degrading, thereby improving the device characteristics and reliability.

    Abstract translation: 半导体器件中的金属线包括形成在半导体衬底上的绝缘层。 在绝缘层中形成金属线形成区域。 在金属线形成区域的表面上形成扩散阻挡层,并且形成金属线以填充绝缘层的金属线形成区域。 在金属线和绝缘层之间形成扩散阻挡层。 扩散阻挡层具有其中TaSixNy层介于第一Ta基层和第二Ta基层之间的结构。 以这种方式形成的金属线防止金属线的接触电阻增加,并且漏电流特性降低,从而提高器件特性和可靠性。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF REDUCING PARASITIC BIT LINE CAPACITANCE
    27.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF REDUCING PARASITIC BIT LINE CAPACITANCE 失效
    制造可降低PARASITIC BIT线电容的半导体器件的方法

    公开(公告)号:US20080146026A1

    公开(公告)日:2008-06-19

    申请号:US11776905

    申请日:2007-07-12

    Abstract: A semiconductor memory device is manufactured by: forming a hole by etching an interlayer insulation film formed over a semiconductor substrate; forming a barrier film over the interlayer insulation film including a surface of the hole; forming a first metal film over the barrier film so as to fill in the hole; forming a bit line contact plug in the hole by removing the first metal film and the barrier film so as to expose the interlayer insulation film; carrying out a gas treatment to a surface of the interlayer insulation film including the bit line contact plug so as to promote a growth of metal nucreation; forming a second metal film over the gas treated interlayer insulation film; and forming a bit line in contact with the bit line contact plug by etching the second metal film.

    Abstract translation: 半导体存储器件通过:通过蚀刻形成在半导体衬底上的层间绝缘膜来形成孔; 在包括所述孔的表面的所述层间绝缘膜上形成阻挡膜; 在所述阻挡膜上形成第一金属膜以填充所述孔; 通过去除第一金属膜和阻挡膜以形成层间绝缘膜,从而在孔中形成位线接触插塞; 对包含位线接触插塞的层间绝缘膜的表面进行气体处理,以促进金属含量的增长; 在气体处理的层间绝缘膜上形成第二金属膜; 并通过蚀刻第二金属膜形成与位线接触插塞接触的位线。

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