利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

66 条记录 (耗时 0.04 秒)

    Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof
    21.
    发明授权
    Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof 失效
    包括短路避免结构的半导体存储装置及其制造方法

    公开(公告)号：US06255686B1

    公开(公告)日：2001-07-03

    申请号：US09124852

    申请日：1998-07-30

    申请人： Hideki Takeuchi ,  Hirohiko Izumi

    发明人： Hideki Takeuchi ,  Hirohiko Izumi

    IPC分类号： H01L27108

    CPC分类号： H01L27/10855 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10885 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor storage device, an access transistor, which has a gate electrode and a pair of impurity diffusion layers, is formed at a device activation region defined by a device isolation structure of a semiconductor substrate. A first insulating film, which has a first contact hole for exposing a portion of the surface of one of the pair of impurity diffusion layers, is formed over the access transistor. A protective film, which has a second contact hole formed on the first contact hole, is formed on the first insulating film. A second insulating film is formed on the side wall faces of the first and second contact holes. A memory capacitor has a lower electrode and an upper part electrode which are opposed each other and are capacitive-coupled through a dielectric film. The lower electrode is filled inside the first and second contact holes to be formed in an island-like shape on the first insulating film through the protective film so as to be electrically connected with the one of the pair of impurity diffusion layers. Each of the first and second contact holes has a diameter which is made smaller by an existence of the second insulating film than a minimum dimension determined by an exposure limit in a photolithography.

    摘要翻译： 在半导体存储装置中，在由半导体衬底的器件隔离结构限定的器件激活区域处形成具有栅电极和一对杂质扩散层的存取晶体管。 在该存取晶体管的上方形成第一绝缘膜，该第一绝缘膜具有用于暴露该对杂质扩散层之一的表面的一部分的第一接触孔。 在第一绝缘膜上形成有形成在第一接触孔上的第二接触孔的保护膜。 第二绝缘膜形成在第一和第二接触孔的侧壁面上。 记忆电容器具有彼此相对并且通过电介质膜电容耦合的下部电极和上部电极。 下部电极填充在第一和第二接触孔的内部，以通过保护膜在第一绝缘膜上形成为岛状，以便与一对杂质扩散层电连接。 第一和第二接触孔中的每一个具有通过第二绝缘膜的存在使得比通过光刻中的曝光极限确定的最小尺寸更小的直径。

    Salt of fused heterocyclic derivative and crystal thereof
    22.
    发明授权
    Salt of fused heterocyclic derivative and crystal thereof 有权
    稠合杂环衍生物的盐及其结晶

    公开(公告)号：US09169266B2

    公开(公告)日：2015-10-27

    申请号：US13577832

    申请日：2011-02-09

    申请人： Kazumichi Jo ,  Hideki Takeuchi

    发明人： Kazumichi Jo ,  Hideki Takeuchi

    IPC分类号： C07D495/04 ,  A61K31/519 ,  A61P15/08 ,  A61P15/16 ,  A61P35/00 ,  A61P15/18 ,  A61P5/24

    CPC分类号： A61K31/519 ,  A61K9/0053 ,  A61K31/14 ,  C07B2200/13 ,  C07D495/04

    摘要： An objective of the present invention is to improve the solubility of 3-[2-fluoro-5-(2,3-difluoro-6-methoxybenzyloxy)-4-methoxyphenyl]-2,4-dioxo-1,2,3,4-tetrahydrothieno[3,4-d]pyrimidine-5-carboxylic acid.The present invention provides 3-[2-fluoro-5-(2,3-difluoro-6-methoxybenzyl-oxy)-4-methoxyphenyl]-2,4-dioxo-1,2,3,4-tetrahydrothieno[3,4-d]pyrimidine-5-carboxylic acid choline salt has excellent solubility and storage stability.

    摘要翻译： 本发明的目的是提高3- [2-氟-5-（2,3-二氟-6-甲氧基苄氧基）-4-甲氧基苯基] -2,4-二氧代-1,2,3,4-四氢 - 4-四氢噻吩并[3,4-d]嘧啶-5-甲酸。 本发明提供3- [2-氟-5-（2,3-二氟-6-甲氧基苄氧基）-4-甲氧基苯基] -2,4-二氧代-1,2,3,4-四氢噻吩并[ 4-d]嘧啶-5-羧酸胆碱盐具有优异的溶解性和储存稳定性。

    Hemifumarate of a pyrazole derivative
    23.
    发明授权
    Hemifumarate of a pyrazole derivative 有权
    吡唑衍生物的半富马酸盐

    公开(公告)号：US08354382B2

    公开(公告)日：2013-01-15

    申请号：US12988273

    申请日：2009-04-13

    申请人： Hideki Takeuchi ,  Eiji Tsuru

    发明人： Hideki Takeuchi ,  Eiji Tsuru

    IPC分类号： A01N43/04 ,  A61K31/70 ,  C07G3/00 ,  C07H15/00 ,  C07H17/00 ,  C07H17/02 ,  C07H23/00

    CPC分类号： C07H17/02

    摘要： The present invention provides a novel form of 3-(3-{4-[3-(β-D-glucopyranosyloxy)-5-isopropyl-1H-pyrazol-4-ylmethyl]-3-methylphenoxy}propylamino)-2,2-dimethylpropionamide with improved storage stability. Since 3-(3-{4-[3-(β-D-glucopyranosyloxy)-5-isopropyl-1H-pyrazol-4-ylmethyl]-3-methylphenoxy}-propylamino)-2,2-dimethylpropionamide hemifumarate dihydrate has extremely excellent storage stability, it is useful as a drug substance. Furthermore, it shows an extremely good crystalline property and can be purified by a convenient method, and therefore is suitable for the industrial preparation.

    摘要翻译： 本发明提供3-（3- {4- [3-（＆bgr。-D-吡喃葡萄糖氧基）-5-异丙基-1H-吡唑-4-基甲基] -3-甲基苯氧基}丙基氨基） 具有改善的储存稳定性的2-二甲基丙酰胺。 由于3-（3- {4- [3-（＆bgr。-D-吡喃葡萄糖氧基）-5-异丙基-1H-吡唑-4-基甲基] -3-甲基苯氧基} - 丙基氨基）-2,2-二甲基丙酰胺半富马酸盐二水合物具有 极好的储存稳定性，作为药物有用。 此外，其显示出非常好的结晶性，并且可以通过方便的方法进行纯化，因此适用于工业制备。

    Damascene process for use in fabricating semiconductor structures having micro/nano gaps
    24.
    发明授权
    Damascene process for use in fabricating semiconductor structures having micro/nano gaps 有权
    用于制造具有微/纳米间隙的半导体结构的镶嵌工艺

    公开(公告)号：US08329559B2

    公开(公告)日：2012-12-11

    申请号：US11737545

    申请日：2007-04-19

    申请人： Hideki Takeuchi ,  Emmanuel P. Quevy ,  Tsu-Jae King ,  Roger T. Howe

    发明人： Hideki Takeuchi ,  Emmanuel P. Quevy ,  Tsu-Jae King ,  Roger T. Howe

    IPC分类号： H01L21/46 ,  H01L21/78 ,  H01L21/301

    CPC分类号： B81C1/00142 ,  B81B2201/0271 ,  B81C2201/0109 ,  Y10S438/933

    摘要： In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.

    摘要翻译： 在制造微机电结构（MEMS）中，在MEMS中形成窄间隙的方法包括：a）在支撑衬底的表面上沉积牺牲材料层，b）光致抗蚀剂掩模并且至少部分蚀刻牺牲材料以形成 至少一个牺牲材料刀片，c）在所述牺牲层上沉积结构层，以及d）去除包括所述牺牲材料刀片的所述牺牲层，其中所述牺牲材料刀片被去除的所述结构层中残留有窄间隙 。

    SUSTAINED RELEASE PREPARATION
    26.
    发明申请
    SUSTAINED RELEASE PREPARATION 审中-公开
    持续发布准备

    公开(公告)号：US20090148480A1

    公开(公告)日：2009-06-11

    申请号：US11995500

    申请日：2006-07-14

    申请人： Nobuyuki Isshiki ,  Noboru Kamada ,  Hideki Takeuchi

    发明人： Nobuyuki Isshiki ,  Noboru Kamada ,  Hideki Takeuchi

    IPC分类号： A61K9/00 ,  A61P1/00

    CPC分类号： A61K9/0065 ,  A61K9/2086 ,  A61K31/341 ,  A61K31/496

    摘要： The invention provides a preparation which shows a satisfactory gastric residence time, has such a size that allows for easy ingestion, can quickly disintegrate after expelled from the stomach, and can be prepared readily in an industrial scale. A gastric retentive preparation having a gastric resident layer and a drug release layer is provided, wherein the gastric resident layer does not disintegrate in the stomach and disintegrates in the intestine. Preferably, the gastric resident layer has a minimum diameter of 7 mm or more as measured after stirring the preparation in the first fluid at 200 rpm at 37° C. for 15 hours under the conditions of the paddle method in the dissolution test in accordance with Japanese Pharmacopoeia and has a maximum diameter of 6 mm or less as measured after further stirring the preparation in the second fluid at 200 rpm at 37° C. for 9 hours under the same conditions.

    摘要翻译： 本发明提供一种显示令人满意的胃停留时间的制剂，具有允许容易摄入的尺寸，可以在从胃排出后迅速崩解，并且可以以工业规模容易地制备。 提供了具有胃滞留层和药物释放层的胃滞留制剂，其中胃停留层在胃中不分解并在肠中分解。 优选地，胃停留层的最小直径为7mm以上，在第一流体中的制剂在200rpm下在37℃下搅拌15小时时，在桨式方法的条件下根据溶出试验按照 日本药典，并且在相同条件下，在第二流体中以200rpm在37℃下进一步搅拌制备9小时后测得的最大直径为6mm或更小。

    Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same
    30.
    发明申请
    Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same 失效

    公开(公告)号：US20060197695A1

    公开(公告)日：2006-09-07

    申请号：US11411143

    申请日：2006-04-26

    申请人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

    发明人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

    IPC分类号： H03M1/12

    CPC分类号： H03K19/00361 ,  H03K17/162

    摘要： The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive. Moreover, a communication circuit for setting the number of data buses to be newly added to be less than two times a transmission on data, then encoding the data to be sent 80 as to make the numbers of “0” and “1” in the data to be sent through the data buses equal to each other and accordingly reducing the increase of the number of the data buses to a minimum and thereby suppressing the common phase power supply noise is provided. A communication apparatus comprising the communication circuit is also provided. Furthermore, the bypass capacitor C for noise suppression circuit is formed in an empty space in a ASIC. A polysilicon layer constituting one electrode of the bypass capacitor is formed in the substrate contact region formed between basic cells regularly arranged, each including a plurality of nMOS and pMOS transistors. This bypass capacitor C is connected between the high and the low level power supply lines to reduce the current running through the power supply line to suppress the EMI noise.