公开(公告)号：US06570215B2

公开(公告)日：2003-05-27

申请号：US10199157

申请日：2002-07-18

申请人： Hsing T. Tuan ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao

发明人： Hsing T. Tuan ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao

IPC分类号： H01L2362

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42336

摘要： In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

公开(公告)号：US20070264779A1

公开(公告)日：2007-11-15

申请号：US11828557

申请日：2007-07-26

申请人： Chia-Shun Hsiao ,  Yi Ding

发明人： Chia-Shun Hsiao ,  Yi Ding

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/66825

摘要： Dielectric regions (210) are formed on a semiconductor substrate between active areas of nonvolatile memory cells. The top portions of the dielectric region sidewalls are etched to recess the top portions laterally away from the active areas. Then a conductive layer is deposited to form the floating gates (410). The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.

摘要翻译： 电介质区域（210）形成在非易失性存储单元的有源区域之间的半导体衬底上。 蚀刻电介质区域侧壁的顶部以将顶部部分横向远离有源区域。 然后沉积导电层以形成浮栅（410）。 电介质侧壁的凹陷部分允许浮动栅极在顶部较宽。 结果，门耦合比增大。 还提供其他功能。

公开(公告)号：US20070085152A1

公开(公告)日：2007-04-19

申请号：US11250822

申请日：2005-10-14

申请人： Douglas Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

发明人： Douglas Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

IPC分类号： H01L29/76

CPC分类号： H01L27/10867 ,  H01L27/0207

摘要： A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.

摘要翻译： 一种缩小面积动态随机存取存储器（DRAM）单元及其制造方法，其中通过沿着第一图案形成侧壁间隔物，通过两个光刻间距占据小于一个光刻间距的区域，以限定活动的第一部分 存储单元的区域和第二正交定向图案，以限定存储单元的有源区域的第二部分，从而为存储单元的列创建梯形有源区域。

公开(公告)号：US20070072387A1

公开(公告)日：2007-03-29

申请号：US11164546

申请日：2005-11-29

申请人： Su-Chen Lai ,  Chia-Shun Hsiao

发明人： Su-Chen Lai ,  Chia-Shun Hsiao

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A method of fabricating a shallow trench isolation structure is provided. A substrate having a patterned pad layer is provided. A part of the substrate is removed by using the patterned pad layer as a mask and a trench is thus formed in the substrate. A first insulation layer is formed on the substrate, the patterned pad layer and the trench. A second insulation layer is formed on the first insulation layer and partially fills into the trench. A third insulation layer is formed on the substrate and fills in the trench. The third insulation layer on the patterned pad layer and the patterned pad layer are removed subsequently.

摘要翻译： 提供一种制造浅沟槽隔离结构的方法。 提供具有图案化衬垫层的衬底。 通过使用图案化衬垫层作为掩模去除衬底的一部分，并且因此在衬底中形成沟槽。 在衬底，图案化衬垫层和沟槽上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层，并且部分地填充到沟槽中。 第三绝缘层形成在衬底上并填充在沟槽中。 图案化垫层和图案化垫层上的第三绝缘层随后被去除。

公开(公告)号：US06962848B2

公开(公告)日：2005-11-08

申请号：US10689908

申请日：2003-10-20

申请人： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

发明人： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

摘要翻译： 为了制造半导体存储器，在半导体衬底上形成一对或多对第一结构。 每个第一结构包括（a）存储器单元的多个浮动栅极和（b）为存储器单元提供控制栅极的第一导电线。 控制门覆盖浮动门。 每对第一结构对应于多个掺杂区域，每个掺杂区域向存储单元提供源极/漏极区域，该存储器单元具有在一个或者结构中的浮动栅极和控制栅极，并且源极/漏极区域到具有浮置和/ 在另一个结构中控制门。 对于每对，形成第二导线，其底表面在两个结构之间延伸并物理地接触对应的第一掺杂区域。 在一些实施例中，第一掺杂区域被绝缘沟槽分开。 第二导线可以形成至少部分地填充两个第一结构之间的区域的导电插塞。

公开(公告)号：US20050196913A1

公开(公告)日：2005-09-08

申请号：US11102329

申请日：2005-04-07

申请人： Chia-Shun Hsiao ,  Yi Ding

发明人： Chia-Shun Hsiao ,  Yi Ding

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L21/8238

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/66825

摘要： Dielectric regions (210) are formed on a semiconductor substrate between active areas of nonvolatile memory cells. The top portions of the dielectric region sidewalls are etched to recess the top portions laterally away from the active areas. Then a conductive layer is deposited to form the floating gates (410). The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.

摘要翻译： 电介质区域（210）形成在非易失性存储单元的有源区域之间的半导体衬底上。 蚀刻电介质区域侧壁的顶部以将顶部部分横向远离有源区域。 然后沉积导电层以形成浮栅（410）。 电介质侧壁的凹陷部分允许浮动栅极在顶部较宽。 结果，门耦合比增大。 还提供其他功能。

公开(公告)号：US06562681B2

公开(公告)日：2003-05-13

申请号：US09881288

申请日：2001-06-13

申请人： Hsing T. Tuan ,  Vei-Han Chan ,  Chung-Wai Leung ,  Chia-Shun Hsiao

发明人： Hsing T. Tuan ,  Vei-Han Chan ,  Chung-Wai Leung ,  Chia-Shun Hsiao

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42336

摘要： In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

公开(公告)号：US5946568A

公开(公告)日：1999-08-31

申请号：US649466

申请日：1996-05-17

申请人： Chia-Shun Hsiao ,  Wei-Jing Wen ,  Wen-Jeng Lin ,  Chung-Chih Wang

发明人： Chia-Shun Hsiao ,  Wei-Jing Wen ,  Wen-Jeng Lin ,  Chung-Chih Wang

IPC分类号： H01L21/02 ,  H01L21/60 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L21/76897 ,  H01L28/82

摘要： A solid state memory fabrication method of DRAM chips with a self-alignment of field plate/BL isolation process includes using oxide-poly-oxide etch followed by oxidation or sidewall deposition (LPTEOS) to isolate the field plate and BL. This process uses a first etchant and a second etchant in etching the BL/N.sup.+ contact in the fabrication process. During the etch of BL/N.sup.+ contact (2C etch), a low selectivity etchant etches away Ploy-3 first. This first etchant is applied for approximately one hundred eighty seconds. And then a second etchant process is performed using a high Si selectivity etchant, which etches a way the residual oxide. The second etchant is applied for approximately ninety seconds. The exposed poly on the sidewall is isolated from the contact hole by oxidation or deposition (LPTEOS). The oxide formed on the substrate during oxidation is etched away by anisotropic etch. The self-alignment of BL/3P is thus achieved. The planar area of 2P can be increased by this method and not be limited by the overlap of 2C/3P.

摘要翻译： 具有场板/ BL隔离工艺的自对准的DRAM芯片的固态存储器制造方法包括使用氧化物 - 多氧化物蚀刻，随后氧化或侧壁沉积（LPTEOS）来隔离场板和BL。 该工艺在制造工艺中使用第一蚀刻剂和第二蚀刻剂来蚀刻BL / N +接触。 在BL / N +接触蚀刻（2C蚀刻）期间，低选择性蚀刻剂首先蚀刻Ploy-3。 该第一蚀刻剂应用大约一百八十秒。 然后使用高Si选择性蚀刻剂进行第二蚀刻工艺，其蚀刻残余氧化物的方式。 第二种蚀刻剂应用大约九十秒。 侧壁上的暴露的聚合物通过氧化或沉积（LPTEOS）与接触孔隔离。 在氧化过程中形成在衬底上的氧化物被各向异性腐蚀蚀刻掉。 因此实现了BL / 3P的自对准。 可以通过这种方法增加2P的平面面积，而不受2C / 3P的重叠的限制。

公开(公告)号：US20080268646A1

公开(公告)日：2008-10-30

申请号：US12168748

申请日：2008-07-07

申请人： Douglas Blaine Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

发明人： Douglas Blaine Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

IPC分类号： H01L21/311

CPC分类号： H01L27/10867 ,  H01L27/0207

摘要： A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.

摘要翻译： 一种缩小面积动态随机存取存储器（DRAM）单元及其制造方法，其中通过沿着第一图案形成侧壁间隔物，通过两个光刻间距占据小于一个光刻间距的区域，以限定活动的第一部分 存储单元的区域和第二正交定向图案，以限定存储单元的有源区域的第二部分，从而为存储单元的列创建梯形有源区域。

公开(公告)号：US07071115B2

公开(公告)日：2006-07-04

申请号：US10772932

申请日：2004-02-04

申请人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

发明人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/44 ,  H01L21/76

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.