公开(公告)号：US20140146231A1

公开(公告)日：2014-05-29

申请号：US13754913

申请日：2013-01-31

Applicant: Liang-Ting Lin ,  Hung-Chun Yang ,  Shan-Tai Chen

Inventor： Liang-Ting Lin ,  Hung-Chun Yang ,  Shan-Tai Chen

IPC: H04N5/66

CPC classification number: H04N5/66 ,  G06F3/1454 ,  G09G5/36 ,  G09G2330/12 ,  G09G2340/0407 ,  G09G2380/12 ,  H04N5/4448 ,  H04N21/43632 ,  H04N21/43635 ,  H04N21/440236 ,  H04N21/440263 ,  H04N21/8153

Abstract: A display apparatus and an image capturing method are provided. The display apparatus includes a receiving unit, a processing unit, a display panel, a display output interface, and a capturing unit. The receiving unit is coupled to a data bus and receives video stream data provided by an external video source. The processing unit is coupled to the data bus and processes the video stream data to generate display data. The display output interface is coupled to the processing unit and the display panel, receives the display data, and drives the display panel to display an image frame. The capturing unit is coupled to the data bus and captures all or part of the image frame according to a capturing command issued by an external device, so as to obtain captured target data. The capturing unit also transmits the captured target data back to the external device.

Abstract translation: 提供了显示装置和图像捕获方法。 显示装置包括接收单元，处理单元，显示面板，显示器输出接口和捕获单元。 接收单元耦合到数据总线并接收由外部视频源提供的视频流数据。 处理单元耦合到数据总线并处理视频流数据以产生显示数据。 显示输出接口耦合到处理单元和显示面板，接收显示数据，并驱动显示面板显示图像帧。 拍摄单元被耦合到数据总线，并且根据由外部设备发出的捕获命令捕获图像帧的全部或部分，以便获得捕获的目标数据。 捕获单元还将捕获的目标数据发送回外部设备。

公开(公告)号：US08520793B2

公开(公告)日：2013-08-27

申请号：US13090272

申请日：2011-04-20

Applicant: Chun-Cheng Lin ,  Ming-Shih Yu

Inventor： Chun-Cheng Lin ,  Ming-Shih Yu

IPC: H03D3/24

CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/091

Abstract: A phase detector includes a first sampling unit, a sampling module and a phase determining module. The first sampling unit is arranged for sampling a first data input signal to generate a first data signal according to a first clock signal. The sampling module includes a second sampling unit and a third sampling unit. The second sampling unit is arranged for sampling a second data input signal to generate a second data signal according to a second clock signal. The third sampling unit is arranged for sampling the second data signal to generate a third data signal according to the first clock signal. The phase determining module is arranged for generating a phase detecting result according to the first data signal and the third data signal.

Abstract translation: 相位检测器包括第一采样单元，采样模块和相位确定模块。 第一采样单元被布置用于对第一数据输入信号进行采样，以根据第一时钟信号产生第一数据信号。 采样模块包括第二采样单元和第三采样单元。 第二采样单元被布置用于对第二数据输入信号进行采样以根据第二时钟信号产生第二数据信号。 第三采样单元被布置用于对第二数据信号进行采样以根据第一时钟信号产生第三数据信号。 相位确定模块被布置成根据第一数据信号和第三数据信号产生相位检测结果。

公开(公告)号：US08345504B2

公开(公告)日：2013-01-01

申请号：US13009240

申请日：2011-01-19

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

IPC: G11C11/40

CPC classification number: G11C11/413 ,  G11C11/412

Abstract: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.

Abstract translation: 提供具有多个单元的随机存取存储器（RAM）。 在一个实施例中，同一列的单元耦合到同一对位线并且与相同的功率控制器相关联。 每个电池有两个逆变器; 电源控制器有两个电源开关。 对于同一列的单元，两个电源开关根据写操作期间位线的数据输入电压分别对每个单元中的两个反相器执行独立的电源电压控制。

公开(公告)号：US08339757B2

公开(公告)日：2012-12-25

申请号：US12762369

申请日：2010-04-19

Applicant: Fu-Yi Tsai ,  Ming-Dou Ker

Inventor： Fu-Yi Tsai ,  Ming-Dou Ker

IPC: H02H9/00

CPC classification number: H02H9/046

Abstract: An ESD protection circuit with multiple domains, which comprises: an ESD protection device, coupled between a first power supplying line and a first ground line; a first internal circuit, having a first terminal coupled to the first power supplying line; a first switch, coupled between a second terminal of the first internal circuit and a second ground line; and a first ESD detection circuit, coupled to the first switch, for detecting an ESD signal, and controls the first switch to be non-conductive when the ESD signal occurs.

Abstract translation: 一种具有多个域的ESD保护电路，包括：耦合在第一供电线路和第一接地线路之间的ESD保护装置; 第一内部电路，具有耦合到第一供电线的第一端子; 第一开关，耦合在第一内部电路的第二端子和第二接地线之间; 以及耦合到所述第一开关的第一ESD检测电路，用于检测ESD信号，并且当所述ESD信号发生时，将所述第一开关控制为不导通。

公开(公告)号：US20120138961A1

公开(公告)日：2012-06-07

申请号：US12961512

申请日：2010-12-07

Applicant: Po-Yao Huang ,  Chia-Yu Jin ,  Yeong-Jar Chang

Inventor： Po-Yao Huang ,  Chia-Yu Jin ,  Yeong-Jar Chang

IPC: H01L31/12 ,  H01L31/18

CPC classification number: G02B6/4292 ,  G02B6/4214 ,  G02B6/4249 ,  G02B6/4251 ,  G02B6/4253 ,  G02B6/4257 ,  G02B6/4274 ,  G02B6/428 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package structure includes a package substrate, at least a chip, solder balls, a light emitting/receiving device, a optical intermediary device and an optical transmission device. The package substrate has a first surface, a second surface, a circuit and solder ball pads, wherein each solder ball pad is electrically connected to the circuit. The chip is disposed on the first surface and electrically connected to the circuit. The solder balls are respectively disposed on the solder ball pads. The light emitting/receiving device is disposed on the package substrate and electrically connected to the circuit. The optical intermediary device is disposed above the light emitting/receiving device. The optical transmission device is inserted in the optical intermediary device, wherein a light emitting by the light emitting/receiving device is emitted to the optical transmission device via the optical intermediary device so that an optical signal is transmitted through the optical transmission device.

Abstract translation: 半导体封装结构包括封装衬底，至少芯片，焊球，发光/接收器件，光中介器件和光传输器件。 封装衬底具有第一表面，第二表面，电路和焊球垫，其中每个焊球焊盘电连接到电路。 芯片设置在第一表面上并电连接到电路。 焊球分别设置在焊球垫上。 发光/接收装置设置在封装基板上并与电路电连接。 光中继装置设置在发光/接收装置的上方。 光传输装置被插入到光中继装置中，其中由发光/接收装置发射的光经由光中介装置发射到光传输装置，使得光信号通过光传输装置传输。

公开(公告)号：US08014482B2

公开(公告)日：2011-09-06

申请号：US11944638

申请日：2007-11-26

Applicant: Kai Huang

Inventor： Kai Huang

IPC: H04L7/00

CPC classification number: H04L7/033 ,  H04L7/0058

Abstract: A signal receiving circuit includes: a sampler, for receiving an analog signal and sampling the analog signal according to a sampling clock to generate a sampling signal; an ADC, coupled to the sampler, for converting the sampling signal to a digital signal; an equalizer, coupled to the ADC, for equalizing the digital signal to generate an equalized digital signal; a quantizer, coupled to the equalizer for quantizing the equalized digital signal to generate a processed digital signal; and a timing recovery circuit, directly connected to the output terminal of the sampler and coupled to the quantizer, for adjusting the timing of the sampling clock according to the processed digital signal and the digital signal. Timing recovery parameter generating circuits are also disclosed.

Abstract translation: 信号接收电路包括：采样器，用于接收模拟信号并根据采样时钟采样模拟信号以产生采样信号; 耦合到采样器的ADC，用于将采样信号转换成数字信号; 均衡器，耦合到ADC，用于均衡数字信号以产生均衡的数字信号; 量化器，耦合到均衡器，用于量化均衡的数字信号以产生经处理的数字信号; 以及定时恢复电路，其直接连接到采样器的输出端并耦合到量化器，用于根据经处理的数字信号和数字信号调整采样时钟的定时。 还公开了定时恢复参数发生电路。

公开(公告)号：US07986290B2

公开(公告)日：2011-07-26

申请号：US12124397

申请日：2008-05-21

Applicant: Cheng-Yong Yang

Inventor： Cheng-Yong Yang

IPC: H02H11/00 ,  H03K19/094

CPC classification number: G09G3/3688 ,  G09G3/3614 ,  G09G2310/0297

Abstract: Output stage and related method applied to source driver/chip of LCD panel. While performing dot polarization inversion for even/odd channels of LCD panel, n-channel and p-channel MOS transistors of symmetric layout are respectively adopted for alternately transmitting a positive polarization signal of higher swing range and a negative polarization signal of lower swing range from corresponding drivers of asymmetric layout to the even/odd channels, such that a layout area for alternating polarizations can be reduced. Also, the invention directly ties inputs of the output drivers to VDD or VSS so as to turn off the drivers for providing high impedance at the even/odd channels when necessary.

Abstract translation: 输出级和相关方法应用于LCD面板的源驱动器/芯片。 在对LCD面板的偶数/奇数通道执行点偏振反转时，分别采用对称布局的n沟道和p沟道MOS晶体管，以交替地传输较高摆动范围的正偏振信号和较低摆幅范围的负极化信号 对应于非偶数/奇数通道布局的驱动器，从而可以减少用于交替偏振的布局区域。 此外，本发明将输出驱动器的输入直接连接到VDD或VSS，以便在必要时关闭驱动器以在偶数/奇数通道提供高阻抗。

公开(公告)号：US20110149449A1

公开(公告)日：2011-06-23

申请号：US12641037

申请日：2009-12-17

Applicant: Chun-Yu Lin ,  Ming-Dou Ker ,  Fu-Yi Tsai

Inventor： Chun-Yu Lin ,  Ming-Dou Ker ,  Fu-Yi Tsai

IPC: H02H9/00

CPC classification number: H01L27/0262

Abstract: An electrostatic discharge (ESD) clamp circuit is provided, which includes a plurality of identical module circuits. The anode of the first module circuit is coupled to the cathode of the ESD clamp circuit. The anode of each of the other module circuits is coupled to the cathode of the previous module circuit. The cathode of the last module circuit is coupled to the ground terminal of the ESD clamp circuit. Each module circuit includes a conduction path and a detection circuit. The detection circuit is coupled to the anode, the cathode and the conduction path of the module circuit. When the rising speed of the voltage at the anode of the module circuit surpasses a threshold value, the detection circuit makes the conduction path conducting.

Abstract translation: 提供了一种静电放电（ESD）钳位电路，其包括多个相同的模块电路。 第一模块电路的阳极耦合到ESD钳位电路的阴极。 每个其他模块电路的阳极耦合到先前模块电路的阴极。 最后一个模块电路的阴极耦合到ESD钳位电路的接地端。 每个模块电路包括导通路径和检测电路。 检测电路耦合到阳极，阴极和模块电路的传导路径。 当模块电路的阳极电压的上升速度超过阈值时，检测电路使导通路径导通。

公开(公告)号：US07852642B2

公开(公告)日：2010-12-14

申请号：US11951539

申请日：2007-12-06

Applicant: Wen-Hao Yu

Inventor： Wen-Hao Yu

IPC: H02M7/10 ,  G05F1/10

CPC classification number: H02M1/36 ,  H02M2001/0012 ,  Y10S323/901

Abstract: A full digital soft-start circuit adapted for a power supply system is provided. The full digital soft-start circuit includes a ring oscillator, a pulse generator, a counter, and a multiplexer. The ring oscillator generates a plurality of clock signals which are different in phase, while equivalent in duty cycle and frequency. The pulse generator generates a plurality of pulse signals with different duty cycles. The counter generates a multi-bit counting signal. The multiplexer determines whether to transmit the pulse signals generated by the pulse generator so as to generate an output pulse which becomes stable as time going on.

Abstract translation: 提供了适用于电源系统的全数字软启动电路。 全数字软启动电路包括环形振荡器，脉冲发生器，计数器和多路复用器。 环形振荡器产生相位不同的多个时钟信号，占空比和频率相等。 脉冲发生器产生具有不同占空比的多个脉冲信号。 计数器产生一个多位计数信号。 多路复用器确定是否发送由脉冲发生器产生的脉冲信号，以便产生随着时间的推移变得稳定的输出脉冲。

公开(公告)号：US07830181B1

公开(公告)日：2010-11-09

申请号：US12555181

申请日：2009-09-08

Applicant: Ting-Chun Huang ,  Kuan-Yu Chen ,  Yuan-Hsun Chang

Inventor： Ting-Chun Huang ,  Kuan-Yu Chen ,  Yuan-Hsun Chang

IPC: H03K5/00

CPC classification number: H03K5/1252

Abstract: A deglitch circuit including signal transmission units is provided. The signal transmission units are connected in serial to form a signal transmission unit string, and a first signal transmission unit of the signal transmission unit string receives a digital signal. Each signal transmission unit includes a first switch, a first delay circuit and a second switch. First and second terminals of the first switch are coupled to a previous signal transmission unit of the signal transmission unit string and an input terminal of the first delay circuit, respectively. The second switch is coupled between an output terminal of the first delay circuit and a first voltage. When the digital signal has a first logic state, the first switch is turned off, and the second switch is turned on. When the digital signal has a second logic state, the first switch is turned on, and the second switch is turned off.

Abstract translation: 提供了包括信号传输单元的去电泳电路。 信号发送单元串联连接形成信号发送单元串，信号发送单元串的第一信号发送单元接收数字信号。 每个信号传输单元包括第一开关，第一延迟电路和第二开关。 第一开关的第一和第二端子分别耦合到信号传输单元串的先前信号传输单元和第一延迟电路的输入端。 第二开关耦合在第一延迟电路的输出端和第一电压之间。 当数字信号具有第一逻辑状态时，第一开关被关闭，并且第二开关被接通。 当数字信号具有第二逻辑状态时，第一开关接通，第二开关断开。