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    Phase detector, phase detecting method, and clock-and-data recovery device
    1.
    发明授权
    Phase detector, phase detecting method, and clock-and-data recovery device 有权
    相位检测器，相位检测方法以及时钟和数据恢复装置

    公开(公告)号：US08520793B2

    公开(公告)日：2013-08-27

    申请号：US13090272

    申请日：2011-04-20

    Applicant: Chun-Cheng Lin ,  Ming-Shih Yu

    Inventor： Chun-Cheng Lin ,  Ming-Shih Yu

    IPC: H03D3/24

    CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/091

    Abstract: A phase detector includes a first sampling unit, a sampling module and a phase determining module. The first sampling unit is arranged for sampling a first data input signal to generate a first data signal according to a first clock signal. The sampling module includes a second sampling unit and a third sampling unit. The second sampling unit is arranged for sampling a second data input signal to generate a second data signal according to a second clock signal. The third sampling unit is arranged for sampling the second data signal to generate a third data signal according to the first clock signal. The phase determining module is arranged for generating a phase detecting result according to the first data signal and the third data signal.

    Abstract translation: 相位检测器包括第一采样单元，采样模块和相位确定模块。 第一采样单元被布置用于对第一数据输入信号进行采样，以根据第一时钟信号产生第一数据信号。 采样模块包括第二采样单元和第三采样单元。 第二采样单元被布置用于对第二数据输入信号进行采样以根据第二时钟信号产生第二数据信号。 第三采样单元被布置用于对第二数据信号进行采样以根据第一时钟信号产生第三数据信号。 相位确定模块被布置成根据第一数据信号和第三数据信号产生相位检测结果。

    PHASE DETECTOR, PHASE DETECTING METHOD, AND CLOCK-AND-DATA RECOVERY DEVICE
    2.
    发明申请
    PHASE DETECTOR, PHASE DETECTING METHOD, AND CLOCK-AND-DATA RECOVERY DEVICE 有权
    相位检测器，相位检测方法和时钟数据恢复装置

    公开(公告)号：US20120269243A1

    公开(公告)日：2012-10-25

    申请号：US13090272

    申请日：2011-04-20

    Applicant: Chun-Cheng Lin ,  Ming-Shih Yu

    Inventor： Chun-Cheng Lin ,  Ming-Shih Yu

    IPC: H04B17/00

    CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/091

    Abstract: A phase detector includes a first sampling unit, a sampling module and a phase determining module. The first sampling unit is arranged for sampling a first data input signal to generate a first data signal according to a first clock signal. The sampling module includes a second sampling unit and a third sampling unit. The second sampling unit is arranged for sampling a second data input signal to generate a second data signal according to a second clock signal. The third sampling unit is arranged for sampling the second data signal to generate a third data signal according to the first clock signal. The phase determining module is arranged for generating a phase detecting result according to the first data signal and the third data signal.

    Abstract translation: 相位检测器包括第一采样单元，采样模块和相位确定模块。 第一采样单元被布置用于对第一数据输入信号进行采样，以根据第一时钟信号产生第一数据信号。 采样模块包括第二采样单元和第三采样单元。 第二采样单元被布置用于对第二数据输入信号进行采样以根据第二时钟信号产生第二数据信号。 第三采样单元被布置用于对第二数据信号进行采样以根据第一时钟信号产生第三数据信号。 相位确定模块被布置成根据第一数据信号和第三数据信号产生相位检测结果。

    Electrical connector assembly
    3.
    发明授权
    Electrical connector assembly 有权

    公开(公告)号：US12149024B2

    公开(公告)日：2024-11-19

    申请号：US17853861

    申请日：2022-06-29

    Applicant: Chun-Cheng Lin ,  Shy-Luen Chern ,  Chih-Hsiang Tang ,  Hong-Wen Lee

    Inventor： Chun-Cheng Lin ,  Shy-Luen Chern ,  Chih-Hsiang Tang ,  Hong-Wen Lee

    IPC: H01R13/62 ,  H01R13/17 ,  H01R13/24 ,  H01R13/502 ,  H01R13/629

    Abstract: An electrical connector assembly including a first connector and a second connector to be mated with each other is provided. The first connector includes a first body, and at least one first terminal and multiple second terminals disposed therein. The second terminals are symmetrically arranged at opposite sides of the first terminal. The second connector includes a second body, at least one third terminal movably disposed in the second body, multiple fourth terminals disposed in the second body and symmetrically arranged at opposite sides of the third terminal, and a driving module electrically connected to at least one of the fourth terminals and structurally connected to the third terminal. In the mating process of the first and second connector, the second terminals and the fourth terminals are electrically connected firstly, to trigger the driving module to move the third terminal to be structurally and electrically connected to the first terminal.

    Apparatus and Methods for Molded Underfills in Flip Chip Packaging
    7.
    发明申请
    Apparatus and Methods for Molded Underfills in Flip Chip Packaging 有权
    倒装芯片包装中模制底层填料的设备和方法

    公开(公告)号：US20130115735A1

    公开(公告)日：2013-05-09

    申请号：US13289719

    申请日：2011-11-04

    Applicant: Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chun-Cheng Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

    Inventor： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chun-Cheng Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

    IPC: H01L21/98 ,  B29C35/08

    CPC classification number: H01L24/97 ,  B29C33/68 ,  B29C43/18 ,  H01L21/563 ,  H01L21/566 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/00

    Abstract: Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed.

    Abstract translation: 用于成型模制底部填料的方法和装置。 公开了一种方法，其包括在第一温度下将倒装芯片衬底加载到模压机的上模追逐和下模追逐中的所选择的一个中; 将模制的底部填充材料定位在上模具和下模具中的至少一个中，同时保持低于模制的底部填充材料的熔融温度的第一温度; 形成密封的模腔并在模腔中产生真空; 将模制的底部填充材料的温度提高到大于熔点的第二温度，以使模制的底部填充材料在形成底部填充层的倒装芯片衬底上流动并形成包覆成型层; 并将所述倒装芯片基板冷却至基本上低于所述模制底部填充材料的熔融温度的第三温度。 公开了一种装置。

    Methods and Apparatus for Thin Die Processing
    10.
    发明申请
    Methods and Apparatus for Thin Die Processing 审中-公开
    薄模加工方法与装置

    公开(公告)号：US20120267423A1

    公开(公告)日：2012-10-25

    申请号：US13089977

    申请日：2011-04-19

    Applicant: Kuei-Wei Huang ,  Wei-Hung Lin ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Bor-Ping Jang ,  Chung-Shi Liu

    Inventor： Kuei-Wei Huang ,  Wei-Hung Lin ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Bor-Ping Jang ,  Chung-Shi Liu

    IPC: B23K1/20 ,  B25J15/06

    CPC classification number: H01L21/6838 ,  H01L24/75

    Abstract: A vacuum tip and methods for processing thin integrated circuit dies. A vacuum tip for attaching to an integrated circuit die is disclosed comprising a vacuum port configured to connect to a vacuum supply on an upper surface and having a bottom surface; and at least one vacuum hole extending through the vacuum tip and exposed at the bottom surface of the vacuum tip; wherein the vacuum tip is configured to physically contact a surface of an integrated circuit die. Methods for processing integrated circuit dies are disclosed.

    Abstract translation: 真空尖端和薄集成电路管芯的处理方法。 公开了一种用于连接到集成电路管芯的真空端头，其包括被构造成连接到上表面上的具有底表面的真空源的真空端口; 以及至少一个真空孔，其延伸穿过真空尖端并暴露在真空尖端的底表面处; 其中所述真空尖端被配置为物理地接触集成电路管芯的表面。 公开了集成电路管芯的处理方法。

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