公开(公告)号：US20250040237A1

公开(公告)日：2025-01-30

申请号：US18358157

申请日：2023-07-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vitor A. Vulcano Rossi ,  Anton V. Tokranov ,  Hong Yu ,  David C. Pritchard

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66

Abstract: An integrated circuit includes a fin having a height and a width under a gate of a selected fin-type field effect transistor (FinFET) that is less than the height and width along a remainder of the fin including under gates and for source/drain regions of other FinFETs. The IC includes a first FinFET having a first gate over a fin having a first height and a first width under the first gate, and a second FinFET in the fin adjacent to the first FinFET. The second FinFET has a second gate over the fin, and the fin has, under the second gate only, a second height less than the first height and a second width less than the first width. The resulting reduced channel height and width for the second FinFET increases gate control and reduces gate leakage, which is beneficial for ultra-low current leakage (ULL) devices.

公开(公告)号：US12211886B1

公开(公告)日：2025-01-28

申请号：US18765489

申请日：2024-07-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Prateek Kumar Sharma ,  Venkata Narayana Rao Vanukuru ,  Kevin K. Dezfulian ,  Kenneth J. Giewont

IPC: H01L21/768 ,  H01L21/764 ,  H01L49/02

Abstract: Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the scaled cavities.

公开(公告)号：US20250031457A1

公开(公告)日：2025-01-23

申请号：US18223780

申请日：2023-07-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  . Ajay ,  Souvick Mitra ,  Kyong Jin Hwang

IPC: H01L27/02

Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including a well, a field-effect transistor including a gate, a source having a doped region in the well, and a drain, and a silicon-controlled rectifier including a doped region in the well.

公开(公告)号：US12205943B2

公开(公告)日：2025-01-21

申请号：US17890725

申请日：2022-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Souvick Mitra ,  Rajendran Krishnasamy

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/735 ,  H01L29/739

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

公开(公告)号：US12205671B2

公开(公告)日：2025-01-21

申请号：US17815273

申请日：2022-07-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Xiaoli Hu ,  Xiaoxiao Li ,  Wei Zhao ,  Yuqing Sun ,  Xueqiang Dai ,  Xiaohua Cheng

IPC: G11C7/14 ,  G11C7/06

Abstract: Embodiments of the disclosure provide a circuit structure and related method to compensate for sense amplifier leakage. A circuit structure according to the disclosure includes a reference voltage generator coupling a supply voltage and a reference line to a sense amplifier. A multiplexer within the reference voltage generator is coupled to the reference line. The multiplexer includes a plurality of transistors each having a gate terminal coupled to ground.

公开(公告)号：US20250022915A1

公开(公告)日：2025-01-16

申请号：US18899522

申请日：2024-09-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ali RAZAVIEH ,  Haiting WANG

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a vertical nanowire channel region and methods of manufacture. The structure includes: a bottom source/drain region; a top source/drain region; a gate structure extending between the bottom source/drain region and the top source/drain region; and a vertical nanowire in a channel region of the gate structure.

公开(公告)号：US12183814B1

公开(公告)日：2024-12-31

申请号：US18615615

申请日：2024-03-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven J. Bentley ,  Francois Hebert ,  Lawrence Selvaraj Susai ,  Johnatan A Kantarovsky ,  Michael Zierak ,  Mark D. Levy ,  John Ellis-Monaghan

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.

公开(公告)号：US20240429237A1

公开(公告)日：2024-12-26

申请号：US18340463

申请日：2023-06-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton TOKRANOV ,  Man GU ,  Eric Scott KOZARSKY ,  George MULFINGER ,  Hong YU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.

公开(公告)号：US12170329B2

公开(公告)日：2024-12-17

申请号：US17692218

申请日：2022-03-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Vvss Satyasuresh Choppalli ,  Rajendran Krishnasamy

IPC: H01L29/78 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

公开(公告)号：US12170313B2

公开(公告)日：2024-12-17

申请号：US18324637

申请日：2023-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L21/763 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.