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    PATTERNING OF 3D NAND PILLARS AND FLYING BUTTRESS SUPPORTS WITH TWO STRIPE TECHNIQUE
    22.
    发明公开
    PATTERNING OF 3D NAND PILLARS AND FLYING BUTTRESS SUPPORTS WITH TWO STRIPE TECHNIQUE 审中-公开

    公开(公告)号：US20230395528A1

    公开(公告)日：2023-12-07

    申请号：US17860021

    申请日：2022-07-07

    申请人： Micron Technology, Inc.

    发明人： Shruti Jain ,  Anton P. Eppich

    IPC分类号： H01L23/00 ,  H01L27/11556 ,  H01L27/11582

    CPC分类号： H01L23/562 ,  H01L27/11582 ,  H01L27/11556

    摘要： A three-dimensional (3D) memory device including a stack of alternating supporting lattice layers and dielectric layers on a substrate, a plurality of memory pillars vertically penetrating the stack, each of the plurality of memory pillars including a plurality of vertically connected replacement gate (RG) memory cells that correspond to the supporting lattice layers, each of the memory pillars having a first square peripheral shape in a horizontal plane parallel to the supporting lattice layers, and a plurality of supporting buttress (SBT) pillars exclusive of any memory cells that are located at outside ends of the plurality of memory pillars and that vertically penetrate the stack, wherein the plurality of memory pillars and the plurality of SBT pillars are laterally connected by the supporting lattice layers.

    METHODS OF FORMING MICROELECTRONIC DEVICES INCLUDING SUPPORT CONTACT STRUCTURES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
    23.
    发明公开
    METHODS OF FORMING MICROELECTRONIC DEVICES INCLUDING SUPPORT CONTACT STRUCTURES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS 审中-公开

    公开(公告)号：US20230395525A1

    公开(公告)日：2023-12-07

    申请号：US17805009

    申请日：2022-06-01

    申请人： Micron Technology, Inc.

    发明人： Yiping Wang ,  Sandra L. Tagg

    IPC分类号： H01L23/00 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

    CPC分类号： H01L23/562 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

    摘要： Methods of forming a microelectronic device includes forming a preliminary stack structure including blocks separated by slots, each block including: tiers each including insulative material and sacrificial material; and live contact openings and support contact openings extending completely through the tiers. A first liner and a second liner are formed over surfaces of the preliminary stack structure. Portions of the second liner and the first liner within the support contact openings are removed without removing additional portions of the second liner and the first liner within the slots and the live contact openings. Fill material is formed within the slots, the live contact openings, and the support contact openings to form sacrificial slot structures, sacrificial contact structures, and support contact structures. The sacrificial contact structures are replaced with conductive contact structures. The sacrificial slot structures are removed, and the sacrificial material of the tiers is replaced with conductive material.

    Memory Circuitry And Method Used In Forming Memory Circuitry
    24.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20230395494A1

    公开(公告)日：2023-12-07

    申请号：US17851393

    申请日：2022-06-28

    申请人： Micron Technology, Inc.

    发明人： Jivaan Kishore Jhothiraman

    IPC分类号： H01L23/528 ,  H01L27/11556 ,  H01L27/11582

    CPC分类号： H01L23/5283 ,  H01L27/11582 ,  H01L27/11556

    摘要： Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs in a first vertical cross-section along a first direction. Insulating material is in the cavity above the flight of stairs. The insulating material comprises first material atop treads of the stairs of the flight of stairs. Individual of the treads comprise conducting material of one of the conductive tiers. Insulative second material of different composition from that of the first material is directly above the first material. The first material has an uppermost surface in the cavity that is below an uppermost surface of the insulative second material in the cavity. Conductive vias extend through the first material and the insulative second material. Individual of the conductive vias are directly above and directly against the conducting material of the respective tread. Other embodiments, including method, are disclosed.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    26.
    发明公开
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230371254A1

    公开(公告)日：2023-11-16

    申请号：US18062169

    申请日：2022-12-06

    申请人： Samsung Electronics Co., Ltd.

    发明人： Donghoon KWON ,  Hyo-Jung Kim ,  Chungki Min ,  Boun Yoon

    IPC分类号： H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

    摘要： A semiconductor device may include a gate stack including insulating patterns and conductive patterns, which are alternately stacked, first block channel structures penetrating the gate stack, second block channel structures penetrating the gate stack, and an isolation structure penetrating the gate stack. The isolation structure may include a block isolation structure, a first word line isolation structure, and a second word line isolation structure. The block isolation structure may include a first side surface connected to a side surface of the first word line isolation structure, and a second side surface connected to a side surface of the second word line isolation structure, and the first block channel structures comprise an intervening channel structure between the first and second side surfaces of the block isolation structure.

    SEMICONDUCTOR DEVICE, MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    27.
    发明公开
    SEMICONDUCTOR DEVICE, MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20230363159A1

    公开(公告)日：2023-11-09

    申请号：US17737756

    申请日：2022-05-05

    申请人： MACRONIX International Co., Ltd.

    发明人： Pi-Shan Tseng

    IPC分类号： H01L27/11582

    CPC分类号： H01L27/11582

    摘要： A memory device may be applicated in a 3D AND flash memory device. The memory device includes a gate stack structure, a doped channel stack structure, a source pillar and a drain pillar, and a plurality of dielectric structures. The gate stack structure is located on a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The doped channel stack structure extends through the gate stack structure. The doped channel stack structure includes a plurality of doped channel rings spaced apart from each other. The source pillar and the drain pillar extend through the doped channel stack structure. The source pillar and the drain pillar are respectively electrically connected to the plurality of doped channel rings. The plurality of dielectric structures are located between the plurality of gate layers and the plurality of doped channel rings.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    29.
    发明公开
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20230345723A1

    公开(公告)日：2023-10-26

    申请号：US17728651

    申请日：2022-04-25

    申请人： Micron Technology, Inc.

    发明人： Yiping Wang ,  Adam W. Saxler ,  Narula Bilik

    IPC分类号： H01L27/11556 ,  H01L27/11582

    CPC分类号： H01L27/11582 ,  H01L27/11556

    摘要： A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conductive material of a lowest of the conductive tiers. Insulating material of the insulative tier that is immediately-directly above the lowest conductive tier is directly against a top of the conductive material of the lowest conductive tier. The insulating material comprises at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulative material. Other embodiments, including method, are disclosed.