公开(公告)号：US07098723B2

公开(公告)日：2006-08-29

申请号：US10470520

申请日：2002-01-25

Applicant: Henrik Hellberg ,  Anders Emericks ,  Håkan Sjödin

Inventor： Henrik Hellberg ,  Anders Emericks ,  Håkan Sjödin

IPC: H03K3/01 ,  G05F1/10 ,  G05F3/02

CPC classification number: H04M3/005 ,  H04M2201/06

Abstract: In a circuit designed to output a varying output voltage, the substrate of the semi-conductor component is connected to a regulator, in particular a switch, connected to a lower potential than the potential of the substrate of the circuit. The circuit can for example be used in a Subscriber Line Interface Circuit (SLIC).

Abstract translation: 在设计成输出变化的输出电压的电路中，半导体部件的基板连接到调节器，特别是开关，其连接到比电路的基板的电位更低的电位。 该电路可以例如在用户线路接口电路（SLIC）中使用。

公开(公告)号：US06909155B2

公开(公告)日：2005-06-21

申请号：US10101162

申请日：2002-03-20

Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe

Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe

IPC: H01L21/331 ,  H01L21/336 ,  H01L21/762 ,  H01L21/77 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/73 ,  H01L29/78 ,  H01L29/786 ,  H04M3/00 ,  H04M3/18

CPC classification number: H01L29/66681 ,  G09G3/28 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66265 ,  H01L29/66674 ,  H01L29/7317 ,  H01L29/7824 ,  H04M3/005 ,  H04M3/18 ,  H04M2201/06

Abstract: An N-channel MOS field-effect transistor on an SOI substrate including a source electrode, drain and gate electrodes both disposed via a field oxide film, a gate oxide film, a high concentration P-type layer, a high concentration N-type layer contacting the source electrode and the gate oxide film, a high concentration N-type layer contacting the drain electrode, a p-body layer contacting the high concentration P-type and N-type layers and the gate oxide film. In this transistor, an N-type layer with a concentration higher than that of a drain region contacting the p-body layer constitutes a region covering at most 95% of the source-drain distance. Further, an N-type region having a concentration from 3×1016/cm3 to 1×1022/cm3 is provided near a buried oxide film under the drain electrode.

Abstract translation: 在SOI衬底上的N沟道MOS场效应晶体管，其包括经由场氧化膜设置的源电极，漏极和栅电极，栅极氧化膜，高浓度P型层，高浓度N型层 与源电极和栅极氧化膜接触，接触漏电极的高浓度N型层，与高浓度P型和N型层接触的p体层和栅氧化膜。 在该晶体管中，具有高于与p体层接触的漏极区域的浓度的N型层构成覆盖源极 - 漏极距离的至多95％的区域。 此外，浓度为3×10 16 / cm 3至1×10 22 / cm 3的N型区域 设置在漏电极下方的埋入氧化膜附近。

公开(公告)号：US20040213161A1

公开(公告)日：2004-10-28

申请号：US10420177

申请日：2003-04-22

Inventor： David S. Nack

IPC: H04L012/26

CPC classification number: H04M3/30 ,  H04M1/2535 ,  H04M7/006 ,  H04M19/08 ,  H04M2201/06 ,  H04M2203/055

Abstract: According to some embodiments, an integrated circuit is powered with link pulse energy.

Abstract translation: 根据一些实施例，集成电路由链路脉冲能量供电。

公开(公告)号：US20030160284A1

公开(公告)日：2003-08-28

申请号：US10393951

申请日：2003-03-24

Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe

IPC: H01L027/01

CPC classification number: H01L29/66681 ,  G09G3/28 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66265 ,  H01L29/66674 ,  H01L29/7317 ,  H01L29/7824 ,  H04M3/005 ,  H04M3/18 ,  H04M2201/06

Abstract: An N-channel MOS field-effect transistor on an SOI substrate including a source electrode, drain and gate electrodes both disposed via a field oxide film, a gate oxide film, a high concentration P-type layer, a high concentration N-type layer contacting the source electrode and the gate oxide film, a high concentration N-type layer contacting the drain electrode, a p-body layer contacting the high concentration P-type and N-type layers and the gate oxide film. In this transistor, an N-type layer with a concentration higher than that of a drain region contacting the p-body layer constitutes a region covering at most 95% of the source-drain distance. Further, an N-type region having a concentration from 3null1016/cm3 to 1null1022/cm3 is provided near a buried oxide film under the drain electrode.

Abstract translation: 在SOI衬底上的N沟道MOS场效应晶体管，其包括经由场氧化膜设置的源电极，漏极和栅电极，栅极氧化膜，高浓度P型层，高浓度N型层 与源电极和栅极氧化膜接触，接触漏电极的高浓度N型层，与高浓度P型和N型层接触的p体层和栅氧化膜。 在该晶体管中，具有高于与p体层接触的漏极区域的浓度的N型层构成覆盖源极 - 漏极距离的至多95％的区域。 此外，在漏电极下方的埋置氧化膜附近设置浓度为3×10 16 / cm 3至1×10 22 / cm 3的N型区域。

公开(公告)号：US06525919B2

公开(公告)日：2003-02-25

申请号：US09862990

申请日：2001-05-22

Applicant: Grady M. Wood

Inventor： Grady M. Wood

IPC: H02H300

CPC classification number: H04M3/18 ,  H04M3/005 ,  H04M2201/06

Abstract: A switch includes first and second switch terminals, at least one output MOS transistor for selectively connecting the first and second switch terminals, and a driving current source for driving the at least one output MOS transistor. The switch may also include a current limiter for limiting the driving of the at least one output MOS transistor by the driving current source to establish a current limit. Furthermore, a controller may be included for the current limiter for controlling the current limit, such as by causing the current limiter to decrease the current limit based upon an increase in temperature of the integrated circuit or at periodic intervals to control rise and fall times of the at least one output MOS transistor.