公开(公告)号：US20220310803A1

公开(公告)日：2022-09-29

申请号：US17653719

申请日：2022-03-07

申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

发明人： Tadashi WATANABE ,  Yukinori NOSE

IPC分类号： H01L29/40 ,  H01L29/20 ,  H01L29/778 ,  H01L21/02 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66

摘要： A semiconductor device includes a substrate, a nitride semiconductor layer formed on the substrate, a source electrode and a drain electrode formed in the nitride semiconductor layer. The source electrode and drain electrode are arranged side by side in a first direction. A gate electrode is formed on the nitride semiconductor layer between the source electrode and the drain electrode. A first protective film is formed on the nitride semiconductor layer, and covers the first protective film covering the source electrode, the drain electrode, and the gate electrode. A source field plate is formed on the first protective film between the gate electrode and the drain electrode in a plan view. A dielectric-breakdown inhibition portion includes a part positioned between an end of the source field plate and an end of the drain electrode in a sectional view, and inhibits dielectric breakdown of the first protective film.

公开(公告)号：US20220293779A1

公开(公告)日：2022-09-15

申请号：US17200916

申请日：2021-03-15

申请人： Vanguard International Semiconductor Corporation

发明人： Yang Du ,  Shin-Chen Lin ,  Chia-Ching Huang

IPC分类号： H01L29/778 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L21/765 ,  H01L29/66

摘要： A high electron mobility transistor includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate field plate, a source electrode, at least one first field plate, and a second field plate. The gate field plate is disposed on the semiconductor barrier layer. The source electrode is disposed on one side of the gate field plate, and the first field plate is disposed on the other side of the gate field plate and laterally spaced apart from the gate field plate. The second field plate covers the gate field plate and the first field plate and is electrically connected to the source electrode, where the area of the second field plate is larger than the sum of the area of the gate field plate and the area of the first field plate when perceived from a top-down perspective.

公开(公告)号：US20220262908A1

公开(公告)日：2022-08-18

申请号：US17735369

申请日：2022-05-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Cheng Ho ,  Hui-Ting Lu ,  Pei-Lun Wang ,  Yu-Chang Jong ,  Jyun-Guan Jhou

IPC分类号： H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/765 ,  H01L21/8238

摘要： Various embodiments of the present disclosure are directed towards an integrated chip comprising a gate electrode disposed on a substrate between a pair of source/drain regions. A dielectric layer is over the substrate. A field plate is disposed on the dielectric layer and laterally between the gate electrode and a first source/drain region in the pair of source/drain regions. The field plate comprises a first field plate layer and a second field plate layer. The second field plate layer extends along sidewalls and a bottom surface of the first field plate layer. The first and second field plate layers comprise a conductive material.

公开(公告)号：US11374119B2

公开(公告)日：2022-06-28

申请号：US16943527

申请日：2020-07-30

申请人： Mitsubishi Electric Corporation

发明人： Koichi Nishi

IPC分类号： H01L29/739 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L21/765

摘要： A semiconductor device according to the present invention includes a semiconductor substrate including at least a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type provided in the upper layer of the third semiconductor layer; a first gate trench extending in the thickness direction through the fourth, third, and second semiconductor layers to the inside of the first semiconductor layer; an interlayer insulating film; a first main electrode provided in contact with the fourth semiconductor layer; and a second main electrode provided on the side opposite the first main electrode. The first gate trench includes a first gate electrode on the lower side and a second gate electrode on the upper side.

公开(公告)号：US20220190156A1

公开(公告)日：2022-06-16

申请号：US17653300

申请日：2022-03-03

申请人： Silanna Asia Pte Ltd

发明人： David Snyder ,  Shanghui Larry Tu

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/765 ,  H01L21/225

摘要： A method for forming a semiconductor device involves providing a semiconductor wafer having an active layer of a first conductivity type. First and second gates having first and second gate polysilicon are formed on the active layer. A first mask region is formed on the active layer. Between the first and second gates, using the first mask region, the first gate polysilicon, and the second gate polysilicon as a mask, a deep well of a second conductivity type, a shallow well of the second conductivity type, a source region of the first conductivity type, and first and second channel regions of the second conductivity type, are formed. In the active layer, using one or more second mask regions, first and second drift regions of the first conductivity type, first and second drain regions of the first conductivity type, and a source connection region of the second conductivity type, are formed.

公开(公告)号：US20220181484A1

公开(公告)日：2022-06-09

申请号：US17542610

申请日：2021-12-06

申请人： Hangzhou Silicon-Magic Semiconductor Technology Co., Ltd.

发明人： Bing Wu ,  Jiakun Wang

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/765 ,  H01L29/66

摘要： Disclosed is a trench-type MOSFET and a method for manufacturing the same. The method comprises: forming a trench in a semiconductor substrate; forming a first insulating layer and a shielding conductor in the trench; forming an opening on two sides of the shielding conductor in the trench, wherein the opening is separated from the shielding conductor by the first insulating layer; forming a gate dielectric layer and a gate conductor in the opening, wherein the trench extends from an upper surface of the semiconductor substrate into the semiconductor substrate, the first insulating layer covers a sidewall and a bottom of the trench and separates the shielding conductor from the semiconductor substrate, the gate dielectric layer at least covers a sidewall of the opening. The method simplifies the process steps of forming the trench-type MOSFET compared with the prior art, and reduces process errors.

公开(公告)号：US20220115391A1

公开(公告)日：2022-04-14

申请号：US17555828

申请日：2021-12-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei-Cheng Wu ,  Li-Feng Teng ,  Chien-Hung Chang

IPC分类号： H01L27/112 ,  H01L21/765 ,  H01L21/762 ,  H01L23/00 ,  H01L27/11524 ,  H01L29/66 ,  H01L27/11546 ,  H01L29/06 ,  H01L29/40 ,  H01L21/28 ,  H01L27/11534

摘要： A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

公开(公告)号：US20220093727A1

公开(公告)日：2022-03-24

申请号：US17163626

申请日：2021-02-01

申请人： SANKEN ELECTRIC CO., LTD. ,  Allegro MicroSystems, LLC

发明人： Taro KONDO

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L21/765 ,  H01L29/66

摘要： A semiconductor device is disclosed including a sub-layer with first conductivity type, a drift layer with first conductivity type, a base region with second conductivity type positioned on the drift layer, a source region in contact with the base region, a source electrode, a plurality of trenches, at least one of the trenches in contact with the drift layer, the base region, and the source region, a plurality of insulating regions, at least one of the insulating regions positioned inside of each trench, a plurality of gate electrodes, at least one of the gate electrodes positioned inside of each trench; and a plurality of field plates, at least one of the field plates electrically connected to the source electrode and positioned in the insulating region in the trench. The field plate comprises high-resistance polysilicon.

公开(公告)号：US20210336047A1

公开(公告)日：2021-10-28

申请号：US17217689

申请日：2021-03-30

申请人： STMicroelectronics Pte Ltd

发明人： Shin Phay LEE ,  Voon Cheng NGWAN ,  Maurizio Gabriele CASTORINA

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L21/765 ,  H01L29/66

摘要： An integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with a body diode of the MOSFET device. The monolithic diode device is configured so that a forward voltage drop VfD2 of the monolithic diode device is less than a forward voltage drop VfD1 of the body diode of the MOSFET device. The forward voltage drop VfD2 is process tunable by controlling a gate oxide thickness, a channel length and body doping concentration level. The tunability of the forward voltage drop VfD2 advantageously permits design of the integrated circuit to suit a wide range of applications according to requirements of switching speed and efficiency.

公开(公告)号：US20210296434A1

公开(公告)日：2021-09-23

申请号：US16859840

申请日：2020-04-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC CHINA COMPANY LIMITED

发明人： Zheng-Long CHEN

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/765 ,  H01L29/66

摘要： A method includes forming a hard mask over an epitaxy layer of a substrate; forming a patterned mask over the hard mask; etching the hard mask and the epitaxy layer to form a trench in the epitaxy layer, in which a remaining portion of the hard mask covers a topmost surface of the epitaxy layer, and the trench exposes a sidewall of the epitaxy layer; forming a P-well region by directing p-type ion beams into the trench along an oblique direction that is non-parallel to a normal line of the topmost surface of the epitaxy layer, in which the topmost surface of the epitaxy layer is protected from the p-type ion beams by the remaining portion of the hard mask during directing the p-type ion beams into the trench; and after directing the p-type ion beams into the trench, forming a gate structure in the trench.