-
公开(公告)号：US11812616B2
公开(公告)日：2023-11-07
申请号：US17533339
申请日：2021-11-23
IPC分类号： H10B43/35 , H01L29/423 , H01L21/28 , H01L21/033 , H01L29/06 , H10B43/50
CPC分类号： H10B43/35 , H01L21/0337 , H01L29/0649 , H01L29/40117 , H01L29/42352 , H10B43/50
摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.
-
公开(公告)号：US11706914B2
公开(公告)日：2023-07-18
申请号：US17555828
申请日：2021-12-20
发明人： Meng-Han Lin , Te-Hsin Chiu , Wei-Cheng Wu , Li-Feng Teng , Chien-Hung Chang
IPC分类号： H01L21/765 , H10B20/00 , H01L21/28 , H01L21/762 , H01L23/00 , H01L29/06 , H01L29/40 , H01L29/66 , H10B41/35 , H10B41/43 , H10B41/49
CPC分类号： H10B20/60 , H01L21/765 , H01L21/76229 , H01L23/562 , H01L29/0649 , H01L29/404 , H01L29/40114 , H01L29/66825 , H10B41/35 , H10B41/43 , H10B41/49
摘要： A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
-
公开(公告)号：US12048163B2
公开(公告)日：2024-07-23
申请号：US18364022
申请日：2023-08-02
IPC分类号： H10B43/35 , H01L21/033 , H01L21/28 , H01L29/06 , H01L29/423 , H10B43/50
CPC分类号： H10B43/35 , H01L21/0337 , H01L29/0649 , H01L29/40117 , H01L29/42352 , H10B43/50
摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.
-
公开(公告)号：US20220359558A1
公开(公告)日：2022-11-10
申请号：US17866922
申请日：2022-07-18
发明人： Wei Cheng Wu , Chien-Hung Chang
IPC分类号： H01L27/11575 , H01L29/06 , H01L21/76 , H01L27/11573 , H01L21/762
摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed on or within a substrate and a plurality of memory devices disposed on or within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. A dummy gate structure is arranged on the first isolation structure and has a top surface that is vertically above top surfaces of the plurality of transistor devices and the plurality of memory devices.
-
公开(公告)号：US20240324229A1
公开(公告)日：2024-09-26
申请号：US18731454
申请日：2024-06-03
IPC分类号： H10B43/35 , H01L21/033 , H01L21/28 , H01L29/06 , H01L29/423 , H10B43/50
CPC分类号： H10B43/35 , H01L21/0337 , H01L29/0649 , H01L29/40117 , H01L29/42352 , H10B43/50
摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC is manufactured by forming a plurality of deep trenches including an isolation trench and a logic device trench from a top surface of a substrate, filling an isolation material in the isolation trench and the logic device trench, removing the isolation material from the logic device trench, forming a first logic device by filling a first logic gate dielectric and a first logic gate electrode in the logic device trench, and forming first and second source/drain regions in the substrate on opposite sides of the logic device trench. The isolation material is kept in the isolation trench to form an isolation structure.
-
公开(公告)号：US20230380171A1
公开(公告)日：2023-11-23
申请号：US18364022
申请日：2023-08-02
IPC分类号： H10B43/35 , H01L21/28 , H01L21/033 , H01L29/06 , H01L29/423 , H10B43/50
CPC分类号： H10B43/35 , H01L29/40117 , H01L21/0337 , H01L29/0649 , H01L29/42352 , H10B43/50
摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.
-
公开(公告)号：US20220085041A1
公开(公告)日：2022-03-17
申请号：US17533339
申请日：2021-11-23
IPC分类号： H01L27/1157 , H01L27/11575 , H01L29/06 , H01L21/033 , H01L29/423 , H01L21/28
摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.
-
公开(公告)号：US12127399B2
公开(公告)日：2024-10-22
申请号：US18323458
申请日：2023-05-25
发明人： Meng-Han Lin , Te-Hsin Chiu , Wei-Cheng Wu , Li-Feng Teng , Chien-Hung Chang
IPC分类号： H01L29/06 , H01L21/28 , H01L21/762 , H01L21/765 , H01L23/00 , H01L29/40 , H01L29/66 , H10B20/00 , H10B41/35 , H10B41/43 , H10B41/49
CPC分类号： H10B20/60 , H01L21/76229 , H01L21/765 , H01L23/562 , H01L29/0649 , H01L29/40114 , H01L29/404 , H01L29/66825 , H10B41/35 , H10B41/43 , H10B41/49
摘要： A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
-
公开(公告)号：US20230301075A1
公开(公告)日：2023-09-21
申请号：US18323458
申请日：2023-05-25
发明人： Meng-Han Lin , Te-Hsin Chiu , Wei-Cheng Wu , Li-Feng Teng , Chien-Hung Chang
IPC分类号： H10B20/00 , H01L21/28 , H01L21/762 , H01L21/765 , H01L23/00 , H01L29/06 , H01L29/40 , H01L29/66 , H10B41/35 , H10B41/43 , H10B41/49
CPC分类号： H10B20/60 , H01L29/40114 , H01L21/76229 , H01L21/765 , H01L23/562 , H01L29/0649 , H01L29/404 , H01L29/66825 , H10B41/35 , H10B41/43 , H10B41/49
摘要： A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
-
公开(公告)号：US20220115391A1
公开(公告)日：2022-04-14
申请号：US17555828
申请日：2021-12-20
发明人： Meng-Han Lin , Te-Hsin Chiu , Wei-Cheng Wu , Li-Feng Teng , Chien-Hung Chang
IPC分类号： H01L27/112 , H01L21/765 , H01L21/762 , H01L23/00 , H01L27/11524 , H01L29/66 , H01L27/11546 , H01L29/06 , H01L29/40 , H01L21/28 , H01L27/11534
摘要： A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.018 秒)
