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公开(公告)号：US20230387020A1
公开(公告)日：2023-11-30
申请号：US17825345
申请日：2022-05-26
IPC分类号： H01L23/532 , H01L23/00 , H01L23/522 , H01L21/768
CPC分类号： H01L23/53295 , H01L24/08 , H01L24/80 , H01L23/5226 , H01L21/76802 , H01L21/76877 , H01L21/76832 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896
摘要： The present disclosure relates to an integrated chip including a first dielectric layer overlying a substrate and a first conductive interconnect within the first dielectric layer. A bonding layer is over the first dielectric layer. The bonding layer includes a bonding dielectric layer and a bonding interconnect in the bonding dielectric layer. A first charged dielectric layer is along a bottom of the first dielectric layer. A second charged dielectric layer is along a top of the first dielectric layer. The first charged dielectric layer and the second charged dielectric layer have a same polarity.
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公开(公告)号：US11706914B2
公开(公告)日：2023-07-18
申请号：US17555828
申请日：2021-12-20
发明人： Meng-Han Lin , Te-Hsin Chiu , Wei-Cheng Wu , Li-Feng Teng , Chien-Hung Chang
IPC分类号： H01L21/765 , H10B20/00 , H01L21/28 , H01L21/762 , H01L23/00 , H01L29/06 , H01L29/40 , H01L29/66 , H10B41/35 , H10B41/43 , H10B41/49
CPC分类号： H10B20/60 , H01L21/765 , H01L21/76229 , H01L23/562 , H01L29/0649 , H01L29/404 , H01L29/40114 , H01L29/66825 , H10B41/35 , H10B41/43 , H10B41/49
摘要： A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
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公开(公告)号：US20230154863A1
公开(公告)日：2023-05-18
申请号：US18155672
申请日：2023-01-17
发明人： Wei-Cheng Wu , Chien-Chia Chiu , Cheng-Hsien Hsieh , Li-Han Hsu , Meng-Tsan Lee , Tsung-Shu Lin
IPC分类号： H01L23/552 , H01L21/56 , H01L21/768 , H01L23/31 , H01L23/488 , H01L23/538 , H01L23/00
CPC分类号： H01L23/552 , H01L21/56 , H01L21/76802 , H01L21/76877 , H01L23/31 , H01L23/488 , H01L23/5384 , H01L24/14
摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
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公开(公告)号：US20230054020A1
公开(公告)日：2023-02-23
申请号：US17981465
申请日：2022-11-06
发明人： Wei-Chih Lai , Chien-Chia Chiu , Chen-Hua Yu , Der-Chyang Yeh , Cheng-Hsien Hsieh , Li-Han Hsu , Tsung-Shu Lin , Wei-Cheng Wu , Yu-Chen Hsu
IPC分类号： H01L23/367 , H01L23/31 , H01L23/538 , H01L21/52 , H01L25/065 , H01L21/56 , H01L25/00 , H01L23/498
摘要： A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.
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公开(公告)号：US20220352060A1
公开(公告)日：2022-11-03
申请号：US17243600
申请日：2021-04-29
发明人： Che-Yu Yeh , Tsung-Shu Lin , Wei-Cheng Wu , Tsung-Yu Chen , Li-Han Hsu , Chien-Fu Tseng
IPC分类号： H01L23/498 , H01L23/48 , H01L25/065 , H01L23/00
摘要： A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
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公开(公告)号：US20220223542A1
公开(公告)日：2022-07-14
申请号：US17148572
申请日：2021-01-14
发明人： Yu-Wei Lin , Chun-Yen Lan , Tzu-Ting Chou , Tzu-Shiun Sheu , Chih-Wei Lin , Shih-Peng Tai , Wei-Cheng Wu , Ching-Hua Hsieh
IPC分类号： H01L23/00 , H01L23/16 , H01L23/367 , H01L23/538 , H01L21/48
摘要： A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.
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公开(公告)号：US20220093526A1
公开(公告)日：2022-03-24
申请号：US17542527
申请日：2021-12-06
发明人： Wei-Cheng Wu , Chien-Chia Chiu , Cheng-Hsien Hsieh , Li-Han Hsu , Meng-Tsan Lee , Tsung-Shu Lin
IPC分类号： H01L23/552 , H01L23/00 , H01L23/488 , H01L21/768 , H01L23/31 , H01L21/56 , H01L23/538
摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
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公开(公告)号：US10950577B2
公开(公告)日：2021-03-16
申请号：US16661636
申请日：2019-10-23
发明人： Cheng-Hsien Hsieh , Li-Han Hsu , Wei-Cheng Wu , Hsien-Wei Chen , Der-Chyang Yeh , Chi-Hsi Wu , Chen-Hua Yu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L25/065 , H01L23/538 , H01L25/00 , H01L25/10 , H01L23/00 , H01L21/56 , H01L23/31 , H01L23/498
摘要： An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
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公开(公告)号：US10833030B2
公开(公告)日：2020-11-10
申请号：US16390814
申请日：2019-04-22
发明人： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chen-Hua Yu , Tsung-Shu Lin , Wei-Cheng Wu
摘要： A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.
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10.发明授权公开(公告)号：US10700045B2
公开(公告)日：2020-06-30
申请号：US16675696
申请日：2019-11-06
发明人： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Wei-Cheng Wu
摘要： Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively. The first opening, the second opening, the third opening, and the fourth opening are physically separated from each other.
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