公开(公告)号：US3879669A

公开(公告)日：1975-04-22

申请号：US42338073

申请日：1973-12-10

申请人： TEKTRONIX INC

发明人： MORIYASU HIRO

IPC分类号： H03K5/08 ,  H03K5/18 ,  H03K3/02 ,  H03K5/153

CPC分类号： H03K5/082

摘要： An amplifier means directly receives an input waveform, and this input waveform is also coupled to a pair of storage means for storing peak values thereof. An adjustable means selects a voltage from a range between such peak values and operates a control circuit means for causing the amplifier means to produce a triggering signal when the input waveform reaches a selected value.

摘要翻译： 放大器装置直接接收输入波形，并且该输入波形也耦合到一对存储其峰值的存储装置。 可调整装置从这种峰值之间的范围内选择电压，并且操作控制电路装置，用于当输入波形达到选定值时使放大器装置产生触发信号。

公开(公告)号：US3875515A

公开(公告)日：1975-04-01

申请号：US37151073

申请日：1973-06-19

申请人： RIXON

发明人： STUART RICHARD L ,  TRETTER STEVEN A

IPC分类号： H04L25/03 ,  H03K5/18

CPC分类号： H04L25/03146

摘要： An automatic equalizer for use in digital data modems employs decision directed feedback to cancel the intersymbol interference caused by symbols which have already been decoded. In an equalizer using a minimum mean-square-error algorithm the channel impulse response of each decoded symbol is subtracted from the delay line to effectively eliminate the effects thereof. Two schemes for impulse response identification are disclosed.

摘要翻译： 用于数字数据调制解调器的自动均衡器采用决策指导反馈来消除由已经解码的符号引起的符号间干扰。 在使用最小均方误差算法的均衡器中，从延迟线中减去每个解码符号的信道脉冲响应，以有效地消除其影响。 公开了用于脉冲响应识别的两种方案。

公开(公告)号：US3835400A

公开(公告)日：1974-09-10

申请号：US38262873

申请日：1973-07-25

申请人： US ARMY

发明人： BRISCOE W

IPC分类号： G01S7/34 ,  H03G3/20 ,  H03K5/18

CPC分类号： H03G3/3073 ,  G01S7/34

摘要： The sequential automatic gain control circuit is an improved AGC circuit that can be used in search and track radars which receive a series of pulse returns from each target. The sequential AGC is well suited for monopulse radars and moving target indication (MTI) processing where gain stability and gain match between channels are required. The maximum input signal levels are sensed by a pair of AGC circuits which alternately provide output levels for a predetermined time. The output signal levels are proportional to the maximum input signal received during the previous pulse return period.

摘要翻译： 顺序自动增益控制电路是可用于搜索和跟踪从每个目标接收一系列脉冲返回的雷达的改进的AGC电路。 顺序AGC非常适合于需要增益稳定性和增益在通道之间匹配的单脉冲雷达和移动目标指示（MTI）处理。 最大输入信号电平由一对AGC电路感测，这些AGC电路在预定时间内交替地提供输出电平。 输出信号电平与上次脉冲返回期间接收的最大输入信号成比例。

公开(公告)号：US3792436A

公开(公告)日：1974-02-12

申请号：US3792436D

申请日：1973-01-04

申请人： HONEYWELL INF SYSTEMS

发明人： KLASHKA J ,  DE VOY D ,  BARLOW G

IPC分类号： G06F12/16 ,  A61K31/355 ,  G06F3/06 ,  G06F11/00 ,  G06F11/10 ,  G11B20/14 ,  G11B20/18 ,  G11B20/20 ,  H03M13/00 ,  G06K5/04 ,  G11B27/36 ,  H03K5/18

CPC分类号： G06F11/10 ,  G11B20/1419 ,  G11B20/18 ,  G11B20/20

摘要： A deskewing buffer system includes a plurality of storage registers each of which include a plurality of storage devices. Pairs of the storage devices provide storage for a single information channel. The devices of each channel further includes circuits for detecting when no information has been stored by an input pair of storage devices of a channel within a bit interval which signals a dropped bit within the channel. The detection circuits are then operative to switch both input storage devices of the channel to the same predetermined state. Thereafter, checking circuits coupled to a last register of the buffer system are operative to check the deskewed contents of the register and generate a signal indicating whether the channel dropped a binary ONE or binary ZERO bit. The signal is then used to transfer selectively the state of one of the pairs of storage devices of the channel to an output register.

摘要翻译： 一种歪斜缓冲系统包括多个存储寄存器，每个存储寄存器包括多个存储设备。 成对的存储设备为单个信息通道提供存储。 每个通道的设备还包括电路，用于检测信号中通道内的丢弃位的位间隔内的信道的输入存储设备对何时没有信息存储的电路。 检测电路然后可操作以将通道的两个输入存储设备切换到相同的预定状态。 此后，检查耦合到缓冲器系统的最后一个寄存器的电路可操作以检查寄存器的偏斜校正内容，并产生指示信道是丢弃二进制1或二进制零位的信号。 然后，该信号用于选择性地将信道的一对存储设备的状态传送到输出寄存器。

公开(公告)号：US3790892A

公开(公告)日：1974-02-05

申请号：US3790892D

申请日：1972-05-18

申请人： NIPPON ELECTRIC CO

发明人： TAN Y ,  RYU T

IPC分类号： H04L7/027 ,  H03K5/18

CPC分类号： H04L7/027 ,  H04L7/0276

摘要： A clock pulse regenerating circuit for stably extracting clock pulses from a signal pulse train having an uneven pulse distribution in the time domain. The regenerating circuit includes circuitry for generating auxiliary clock pulses corresponding to recycled previously extracted clock pulses when the signal pulse train lacks pulses for a predetermined time interval.

摘要翻译： 一种用于从时域中具有不均匀脉冲分布的信号脉冲串稳定地提取时钟脉冲的时钟脉冲再生电路。 再生电路包括用于当信号脉冲串缺少脉冲达预定时间间隔时产生对应于再循环的先前提取的时钟脉冲的辅助时钟脉冲的电路。

公开(公告)号：US3783396A

公开(公告)日：1974-01-01

申请号：US3783396D

申请日：1972-03-08

申请人： SCHENCK GMBH CARL

发明人： WAWRA C ,  CHUDEY I

IPC分类号： G01N3/06 ,  H03K5/18 ,  H03B3/02

CPC分类号： G01N3/06

摘要： The present circuit arrangement controls the transmitting of signals, for example, rated control signals, in accordance with predetermined transmittal requirements as represented by the signals to be transmitted, for example, by their amplitudes. For this purpose a signal path is provided for each signal between respective input and output terminals. Switching means in each signal path controlled by signal responsive control means are provided to block or close the respective signal path in accordance with the instantaneous transmittal requirement.

摘要翻译： 本电路装置根据例如由其幅度发射的信号所表示的预定传输要求来控制信号的传输，例如额定控制信号。 为此，为相应的输入和输出端之间的每个信号提供信号路径。 提供由信号响应控制装置控制的每个信号路径中的切换装置，以根据瞬时传输要求阻塞或关闭相应的信号路径。

公开(公告)号：US3758792A

公开(公告)日：1973-09-11

申请号：US3758792D

申请日：1972-09-05

申请人： RCA CORP

发明人： HEUNER R ,  STEUDAL G

IPC分类号： H03K5/1532 ,  H03K5/18 ,  H03K17/60

CPC分类号： H03K5/1532

摘要： A circuit which changes state to produce a different output signal level at the peak of a substantially periodically varying analog input signal whereby the peak of the input signal is detected and indicated.

摘要翻译： 改变状态以在基本周期性变化的模拟输入信号的峰值处产生不同输出信号电平的电路，由此检测和指示输入信号的峰值。

公开(公告)号：US3735271A

公开(公告)日：1973-05-22

申请号：US3735271D

申请日：1971-10-22

申请人： US NAVY

发明人： LEIBOWITZ L

IPC分类号： G01R29/027 ,  H03K5/18

CPC分类号： G01R29/0273

摘要： Two one-shot circuits are triggered by an input data pulse to be interrogated. At the leading edge of the input pulse, one of the two one-shot circuits generates a pulse of the specified width minus the specified tolerance. The other one-shot circuit generates a pulse width equal to the specified tolerance at the trailing edge of the interrogated pulse. The output of the first one-shot circuit triggers a third one-shot circuit which in turn generates a pulse of a width equal to twice the specified tolerance. The outputs of the second and third one-shot circuits are combined in a NAND gate which generates the detection pulse to indicate that the interrogated pulse is within the specified tolerance. The detection pulse is generated as soon as the trailing edge of the interrogated pulse is received. Thus, two input data pulses can be placed as close together as possible as long as the individual pulse identity is maintained, making it possible to maximize the date rate. A multiplicty of detector circuits may be connected in a parallel manner, each generating a detection pulse upon the reception of a pulse specified length, thus permitting the decoding of an entire pulse-width-coded message.

摘要翻译： 两个单触发电路由要询问的输入数据脉冲触发。 在输入脉冲的前沿，两个单触发电路中的一个产生指定宽度的脉冲减去指定的公差。 另一个单触发电路在询问脉冲的后沿产生等于指定公差的脉冲宽度。 第一单触发电路的输出触发第三个单触发电路，该电路又产生一个宽度等于规定公差的两倍的脉冲。 第二和第三单触发电路的输出组合在产生检测脉冲的“与非”门中，以指示询问脉冲在规定的公差内。 一旦接收到询问脉冲的后沿，就产生检测脉冲。 因此，只要维持单独的脉冲识别，就可以将两个输入数据脉冲尽可能靠近放置，使得可以使日期速率最大化。 检测器电路的倍数可以以并行方式连接，每个检测器电路在接收到脉冲指定长度时产生检测脉冲，从而允许对整个脉冲宽度编码消息进行解码。

公开(公告)号：US3735157A

公开(公告)日：1973-05-22

申请号：US3735157D

申请日：1972-01-26

申请人： BOEING CO

发明人： WHETHAM W

IPC分类号： B23B47/20 ,  G05B19/416 ,  G06G7/20 ,  H03K5/18

CPC分类号： G06G7/20 ,  G05B19/4163 ,  G05B2219/35447 ,  G05B2219/37357 ,  G05B2219/41118 ,  G05B2219/43158 ,  G05B2219/49177 ,  G05B2219/50031 ,  Y10T409/300896 ,  Y10T409/3098

摘要： An improved system is provided for sensing spindle deflection of a milling machine and developing a feedrate control signal in accordance therewith to achieve optimum tool life consistant with high metal removal rate from a workpiece. A plurality of magnetic transducers are disposed adjacent the spindle or spindles of a milling machine, and each magnetic transducer is excited by an audio frequency signal such that, as deflection of a spindle brings the spindle closer to or moves it further from a transducer, a corresponding change in the impedance characteristics of the transducer is utilized to develop an a-c signal of a given amplitude. Signals developed from opposing transducers are fed to a differential amplifier to derive a difference signal which is demodulated by a phase detector, rectified and filtered, and then passed through a squaring circuit in order that signals corresponding to the square of the deflection sensed by each transducer pair may be mixed to provide a d-c voltage representing the sum of the squares representing the deflection components. The square root of the sum of the squares is then taken to give a feedback signal proportional to the vector sum of spindle deflection for utilization as a feedrate correction signal. For milling machines utilizing multiple spindles simultaneously, a peak detector circuit is utilized to select the largest sum of the squares only for subsequent development of the feedrate correction signal. Changes in the resistance of the magnetic transducers due to temperature variations encountered under normal operating conditions are compensated by placing the coil of each magnetic transducer in a series circuit which includes a field effect transistor biased to perform as a variable resistor responsive to a change in current flow through the coil by presenting an apparent resistance which opposes the change in current. Runout, which introduces an invalid deflection signal component by modulating the audio frequency reference signal according to the rate of spindle rotation, is compensated by observing the signal produced by runout from each tool holder, tool combination prior to machining, and then providing a continuous equal and opposite signal thereby leaving only the component due to actual spindle deflection. This signal also compensates for component drift. This function is carried out by a loop including a d-c amplifier which drives an A-D converter which, in turn drives a D-A converter which has its output coupled back to the input of the d-c amplifier. When activated, the calibrate circuit introduces trial signal levels until the output of the d-c amplifier is zero, thus negating the effect of runout.

公开(公告)号：US3713010A

公开(公告)日：1973-01-23

申请号：US3713010D

申请日：1971-07-06

申请人： EX CELL O CORP

发明人： DRUSHEL R

IPC分类号： B23H3/02 ,  H03K5/18 ,  H03K5/20

CPC分类号： B23H3/02

摘要： A HIGHLY SENSITIVE AND COMPLETELY STABLE CIRCUIT FOR AND METHOD OF DETECTING LOW AMPLITUDE, SHORT DURATION DIRECT CURRENT SIGNAL VARIATIONS ASSOCIATED WITH SPARKING BETWEEN AN ELECTRODE TOOL AND A CONDUCTING WORKPIECE IN AN ELECTROCHEMICAL MACHINING PROCESS OR THE LIKE AND SUBSTANTIALLY IMMEDIATELY PRODUCING A CONTROL SIGNAL IN RESPONSE TO A PREDETERMINED DETECTED SIGNAL LEVEL IS DISCLOSED. THE STRUCTURE INCLUDES A POLARITY DISCRIMINATING SENSING CIRCUIT FOR INITIALLY DETECTING THE SIGNAL VARIATIONS, AN AMPLIFIER CIRCUIT FOR PROVIDING AN AMPLIFIED AND STABILIZED SIGNAL SUBSTANTIALLY IMMEDIATELY ON SENSING A SIGNAL VARIATION OF THE PROPER POLARITY AND OUTPUT CIRCUIT FOR PROVIDING AN OUTPUT SIGNAL IN RESPONSE TO A SELECTED PORTION OF THE AMPLIFIED AND STABILIZED SIGNAL, INCLUDING MEANS FOR SELECTING THE LEVEL OF THE SELECTED SIGNAL PORTION OPERABLE TO PROVIDE THE OUTPUT SIGNAL, MEANS FOR CUTTING OFF THE AMPLIFIED AND STABILIZED SIGNAL WHEN THE SELECTED LEVEL IS BELOW A PREDETERMINED MINIMUM AND MEANS RESPONSIVE TO A NUMBER OF AMPLIFIED AND STABILIZED SIGNALS, WHICH HAVE A LEVEL BELOW THE SELECTED LEVEL RECEIVED IN A PREDETERMINED TIME FOR PROVIDING AN OUTPUT SIGNAL.