Method of measuring an alignment mark or an alignment mark assembly, alignment system, and lithographic tool

    公开(公告)号:US11442372B2

    公开(公告)日:2022-09-13

    申请号:US17442951

    申请日:2020-02-25

    Abstract: The invention provides a method of measuring an alignment mark or an alignment mark assembly, wherein the alignment mark comprises grid features extending in at least two directions, the method comprising: measuring the alignment mark or alignment mark assembly using an expected location of the alignment mark or alignment mark assembly, determining a first position of the alignment mark or alignment mark assembly in a first direction, determining a second position of the alignment mark or alignment mark assembly in a second direction, wherein the second direction is perpendicular to the first direction, determining a second direction scan offset between the expected location of the alignment mark or alignment mark assembly in the second direction and the determined second position, and correcting the first position on the basis of the second direction scan offset using at least one correction data set to provide a first corrected position.

    METROLOGY SYSTEM AND METHOD
    293.
    发明申请

    公开(公告)号:US20220283515A1

    公开(公告)日:2022-09-08

    申请号:US17637156

    申请日:2020-08-25

    Abstract: A method of determining an overlay measurement associated with a substrate and a system to obtain an overlay measurement associated with a patterning process. A method for determining an overlay measurement may be used in a lithography patterning process. The method includes generating a diffraction signal by illuminating a first overlay pattern and a second overlay pattern using a coherent beam. The method also includes obtaining an interference pattern based on the diffraction signal. The method further includes determining an overlay measurement between the first overlay pattern and the second overlay pattern based on the interference pattern.

    METHOD AND APPARATUS FOR CONTROLLING A COMPUTING PROCESS

    公开(公告)号:US20220283511A1

    公开(公告)日:2022-09-08

    申请号:US17751110

    申请日:2022-05-23

    Abstract: A method of controlling a computer process for designing or verifying a photolithographic component, the method including building a source tree including nodes of the process, including dependency relationships among the nodes, defining, for some nodes, at least two different process conditions, expanding the source tree to form an expanded tree, including generating a separate node for each different defined process condition, and duplicating dependent nodes having an input relationship to each generated separate node, determining respective computing hardware requirements for processing the node, selecting computer hardware constraints based on capabilities of the host computing system, determining, based on the requirements and constraints and on dependency relations in the expanded tree, an execution sequence for the computer process, and performing the computer process on the computing system.

    SUBSTRATE HOLDER, LITHOGRAPHIC APPARATUS AND METHOD

    公开(公告)号:US20220283505A1

    公开(公告)日:2022-09-08

    申请号:US17636411

    申请日:2020-07-07

    Abstract: A substrate holder for supporting a substrate, a lithographic apparatus having the substrate holder and a method of supporting the substrate. The substrate holder includes a main body, a plurality of supporting pins, and a plate. The plate is positioned between a surface of the main body and a support surface formed by the plurality of supporting pins. The plate is actuatable in a direction along the plurality of supporting pins between the surface of the main body and the support surface. The substrate holder may also include a main body, a flexible member and a fixed member protruding from a surface of the main body. The flexible member defines an enclosed cavity therein and configured to form a seal with the substrate supported on the substrate holder. The substrate holder is configured to reduce pressure in the enclosed cavity of the flexible member.

    METHOD, APPARATUS, AND SYSTEM FOR WAFER GROUNDING

    公开(公告)号:US20220277926A1

    公开(公告)日:2022-09-01

    申请号:US17753298

    申请日:2020-08-25

    Abstract: Systems and methods for wafer grounding and wafer grounding location adjustment are disclosed. A first method may include receiving a first value of an electric characteristic associated with the wafer being grounded by an electric signal; determining a first control parameter using at least the first value; and controlling a characteristic of the electric signal using the first control parameter and the first value. A second method for adjusting a grounding location for a wafer may include terminating an electric connection between the wafer and at least one grounding pin in contact the wafer; adjusting a relative position between the wafer and the grounding pin; and restoring the electric connection between the grounding pin and the wafer. A third method may include causing a grounding pin to penetrate through a coating on the wafer by impact; and establishing an electrical connection between the grounding pin and the wafer.

    METHOD AND SYSTEM FOR DETERMINING INFORMATION ABOUT A TARGET STRUCTURE

    公开(公告)号:US20220276569A1

    公开(公告)日:2022-09-01

    申请号:US17629053

    申请日:2020-07-17

    Abstract: Methods and systems for determining information about a target structure are disclosed. In one arrangement, a value of an asymmetry indicator for the target structure is obtained. The value of the asymmetry indicator represents an amount of an overlay independent asymmetry in the target structure. An error in an initial overlay measurement performed on the target structure at a previous time is estimated. The estimation is performed using the obtained value of the asymmetry indicator and a relationship between values of the asymmetry indicator and overlay measurement errors caused at least partially by overlay independent asymmetries. An overlay in the target structure is determined using the initial overlay measurement and the estimated error.

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