公开(公告)号：US20220131215A1

公开(公告)日：2022-04-28

申请号：US17569016

申请日：2022-01-05

Applicant: STMicroelectronics (Tours) SAS

Inventor： Vincent JARRY

IPC: H01M50/10 ,  H01M10/04 ,  H01M6/40 ,  H01M50/116 ,  H01M50/124 ,  H01M50/528 ,  H01M50/543

Abstract: An electronic device includes a base substrate with a mica substrate thereon. A top face of the mica substrate has a surface area smaller than a surface area of a top face of the base substrate. An active battery layer is on the mica substrate and has a top face with a surface area smaller than a surface area of a top face of the mica substrate. An adhesive layer is over the active battery layer, mica substrate, and base substrate. An aluminum film layer is over the adhesive layer, and an insulating polyethylene terephthalate (PET) layer is over the aluminum film layer. A battery pad is on the mica substrate adjacent the active battery layer, and a conductive via extends to the battery pad. A conductive pad is connected to the conductive via. The adhesive, aluminum film, and PET have a hole defined therein exposing the conductive pad.

公开(公告)号：US20220103062A1

公开(公告)日：2022-03-31

申请号：US17548754

申请日：2021-12-13

Applicant: STMicroelectronics (Tours) SAS ,  STMicroelectronics LTD

Inventor： Ghafour BENABDELAZIZ ,  Laurent GONTHIER

IPC: H02M1/42 ,  H02M7/155 ,  H02M7/217

Abstract: An AC capacitor is coupled to a totem-pole type PFC circuit. In response to detection of a power input disconnection, the PFC circuit is controlled to discharge the AC capacitor. The PFC circuit includes a resistor and a first MOSFET and a second MOSFET coupled in series between DC output nodes with a common node coupled to the AC capacitor. When the disconnection event is detected, one of the first and second MOSFETs is turned on to discharge the AC capacitor with a current flowing through the resistor and the turned on MOSFET. Furthermore, a thyristor may be simultaneously turned on, with the discharge current flowing through a series coupling of the MOSFET, resistor and thyristor. Disconnection is detected by detecting a zero-crossing failure of an AC power input voltage or lack of input voltage decrease or input current increase in response to MOSFET turn on for a DC input.

公开(公告)号：US11271561B2

公开(公告)日：2022-03-08

申请号：US16879561

申请日：2020-05-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ghafour Benabdelaziz ,  Cedric Reymond

IPC: H03K17/56 ,  H02M7/06 ,  H02P27/04 ,  H02M5/257 ,  H03K17/725 ,  H02M1/08 ,  H02M7/155 ,  H03K17/722 ,  H03K17/74

Abstract: A thyristor or triac control circuit includes a first capacitive element that is series-connected with a first diode between a first terminal and a second terminal intended to be coupled to a gate of the thyristor or triac. A second capacitive element is coupled between the second terminal and a third terminal intended to be connected to a conduction terminal of the thyristor or triac on the gate side of the thyristor or triac. A second diode is coupled between the third terminal and a node of connection of the first capacitive element and first diode.

公开(公告)号：US20220069110A1

公开(公告)日：2022-03-03

申请号：US17412556

申请日：2021-08-26

Applicant: STMicroelectronics (Tours) SAS

Inventor： Frederic GAUTIER

IPC: H01L29/739 ,  H01L27/07 ,  H01L29/872

Abstract: A device includes a controllable current source connected between a first node and a first terminal coupled to a cathode of a controllable diode. A capacitor is connected between the first node and a second terminal coupled to an anode of the controllable diode. A first switch is connected between the first node and a third terminal coupled to a gate of the controllable diode. A second switch is connected between the second and third terminals. A first diode is connected between the third terminal and the second terminal, an anode of the first diode being preferably coupled to the third terminal.

公开(公告)号：US11152783B2

公开(公告)日：2021-10-19

申请号：US16358964

申请日：2019-03-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mathieu Rouviere

IPC: H02H9/04 ,  H01L27/02 ,  H01L27/06

Abstract: A circuit for protecting against electrostatic discharges includes two avalanche circuit components having different turn-on delays with respect to a beginning of an electrostatic discharge. The two avalanche circuit components are coupled in parallel. The avalanche circuit component closer to an output node has a turn-on delay on the order of 30 ns, while the avalanche circuit component closer to an input node has a turn-on delay on the order of 1 ns.

公开(公告)号：US20210175094A1

公开(公告)日：2021-06-10

申请号：US17104869

申请日：2020-11-25

Applicant: STMicroelectronics (Tours) SAS

Inventor： Michael DE CRUZ ,  Olivier ORY

IPC: H01L21/48 ,  H01L21/56

Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

公开(公告)号：US11025219B2

公开(公告)日：2021-06-01

申请号：US16258883

申请日：2019-01-28

Applicant: STMicroelectronics (Tours) SAS

Inventor： Joel Concord

IPC: H03H7/42 ,  H03H7/01 ,  H03H7/09 ,  H01P1/20 ,  H01P1/203 ,  H03H1/00

Abstract: A filtering circuit includes at least two common-mode filters that are electrically coupled in series and magnetically coupled. The first common-mode filter includes first and second spiral inductors that are positively magnetically coupled and electrically isolated from each other. The second common-mode filter includes third and fourth spiral inductors that are positively magnetically coupled and electrically isolated from each other. The first and third spiral inductors are electrically connected in series and negatively magnetically coupled. Likewise, the second and fourth spiral inductors are electrically connected in series and negatively magnetically coupled.

公开(公告)号：US20210151347A1

公开(公告)日：2021-05-20

申请号：US16950787

申请日：2020-11-17

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic FALLOURD

IPC: H01L21/762 ,  H01L21/56 ,  H01L21/02

Abstract: The present disclosure relates to a method for manufacturing electronic chips. The method includes forming a plurality of trenches on a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed. The trenches delimit laterally a plurality of chips, and each of the chips includes a single integrated circuit. The method further includes electrically isolating flanks of each of the chips by forming an electrically isolating layer on lateral walls of the trenches.

公开(公告)号：US10916939B2

公开(公告)日：2021-02-09

申请号：US16149614

申请日：2018-10-02

Applicant: STMicroelectronics (Tours) SAS ,  STMicroelectronics Asia Pacific Pte Ltd

Inventor： Romain Pichon ,  Yannick Hague ,  Sean Choi

IPC: H02H9/04 ,  H02H9/00 ,  H01C7/108 ,  H01C7/12

Abstract: Transient overvoltage suppression is provided by discharging through a Metal Oxide Varistor (MOV) and Silicon Controlled Rectifier (SCR) which are connected in series between power supply lines. The SCR has a gate that receives a trigger signal generated by a triggering circuit coupled to the power supply lines. A trigger voltage of the triggering circuit is set by a Transil™ avalanche diode.

公开(公告)号：US10903311B2

公开(公告)日：2021-01-26

申请号：US16197011

申请日：2018-11-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Frédéric Lanois ,  Alexei Ankoudinov ,  Vladimir Rodov

IPC: H01L27/06 ,  H01L29/86 ,  H01L29/06 ,  H01L29/861 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H02M3/158 ,  H01L27/092

Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.