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公开(公告)号：US11442700B2
公开(公告)日：2022-09-13
申请号：US16833340
申请日：2020-03-27
Inventor： Michele Rossi , Giuseppe Desoli , Thomas Boesch , Carmine Cappetta
Abstract: A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.
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公开(公告)号：US11436162B2
公开(公告)日：2022-09-06
申请号：US16881949
申请日：2020-05-22
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
Inventor： Riccardo Gemelli , Denis Dutey , Om Ranjan
Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.
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公开(公告)号：US20220271740A1
公开(公告)日：2022-08-25
申请号：US17676005
申请日：2022-02-18
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Marco VITI
Abstract: A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin. The control circuitry is further configured to selectively couple at least one of the second input pins and the reference input pin to the output pin during falling transitions of the pulsed output signal between two positive voltage levels, and selectively couple at least one of the first input pins and the reference input pin to the output pin during rising transitions of the pulsed output signal between two negative voltage levels.
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公开(公告)号：US20220269627A1
公开(公告)日：2022-08-25
申请号：US17673677
申请日：2022-02-16
Applicant: STMicroelectronics S.r.l.
IPC: G06F13/362 , G06F1/12
Abstract: In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. A selection line for each one of the slave devices couples the master device with a respective slave device and is dedicated to selection by the master device of the respective slave device for communication over the shared data communication bus. Each of the slave devices is able to send an interrupt request to the master device over the respective selection line to be served by the master device initiating a communication over the shared data communication bus, each selection line thereby being a bidirectional communication line between the respective slave device and the master device.
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295.发明申请公开(公告)号：US20220263509A1
公开(公告)日：2022-08-18
申请号：US17671844
申请日：2022-02-15
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele MANGANO , Alessandro INGLESE
IPC: H03K19/0175 , G06F13/12
Abstract: A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.
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Patent Agency Ranking
公开(公告)号：US20220263481A1
公开(公告)日：2022-08-18
申请号：US17665399
申请日：2022-02-04
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto MODAFFARI , Germano NICOLLINI
IPC: H03F3/45
Abstract: A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.
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公开(公告)号：US11418888B2
公开(公告)日：2022-08-16
申请号：US16749579
申请日：2020-01-22
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Fabrizio Cerini , Enri Duqi , Silvia Adorno , Lorenzo Baldo
Abstract: An actuation structure of a MEMS electroacoustic transducer is formed in a die of semiconductor material having a monolithic body with a front surface and a rear surface extending in a horizontal plane x-y plane and defined in which are: a frame; an actuator element arranged in a central opening defined by the frame; cantilever elements, coupled at the front surface between the actuator element and the frame; and piezoelectric regions arranged on the cantilever elements and configured to be biased to cause a deformation of the cantilever elements by the piezoelectric effect. A first stopper arrangement is integrated in the die and configured to interact with the cantilever elements to limit a movement thereof in a first direction of a vertical axis orthogonal to the horizontal plane, x-y plane towards the underlying central opening.
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公开(公告)号：US11407098B2
公开(公告)日：2022-08-09
申请号：US16696772
申请日：2019-11-26
Applicant: STMICROELECTRONICS S.R.L. , STMICROELECTRONICS, INC.
Inventor： Marco Bianco , Lorenzo Bracco , Mahesh Chowdhary , Roberto Mura , Stefano Paolo Rivolta , Federico Rizzardini
Abstract: A device for generating a control signal based on the linear movement of a linear member is provided. The device includes a linear member, a rotatable member, a first inertial measurement unit (IMU) coupled to the rotatable member and a second IMU having a fixed position. The device also includes a processing circuit which uses sensing signals from the IMUS to determine an attitude of the first IMU referenced to the second IMU and generate a control signal based on the attitude.
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299.发明申请公开(公告)号：US20220246723A1
公开(公告)日：2022-08-04
申请号：US17579474
申请日：2022-01-19
Applicant: STMicroelectronics S.r.l.
Inventor： Mario Giuseppe SAGGIO , Alessia Maria FRAZZETTO , Edoardo ZANETTI , Alfio GUARNERA
Abstract: A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.
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公开(公告)号：US20220219544A1
公开(公告)日：2022-07-14
申请号：US17711543
申请日：2022-04-01
Applicant: STMicroelectronics S.r.l.
Inventor： Orazio Pennisi , Valerio Bendotti , Vittorio D'Angelo , Paolo Turbanti
Abstract: A method can be used to control a battery management system. A first voltage drop is sensed between a first terminal of a first battery cell and a second terminal of the first battery cell and a second voltage drop is sensed between a first terminal of a second battery cell and a second terminal of the second battery cell. A faulty condition is detected in the first battery cell or the second battery cell based on the first voltage drop or the second voltage drop. The first voltage drop is swapped for a first swapped voltage drop between a common terminal and the second terminal of the second battery cell.
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