公开(公告)号：US20210240445A1

公开(公告)日：2021-08-05

申请号：US16776909

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hemant M. Dixit ,  Julien Frougier ,  Bipul C. Paul ,  William J. Taylor, JR.

IPC: G06F7/58 ,  G11C11/16

Abstract: Embodiments of the disclosure provide a system for providing a true random number (TRN) or physically unclonable function (PUF), including: an array of voltage controlled magnetic anisotropy (VCMA) cells; a voltage pulse tuning circuit for generating and applying a stochastically tuned voltage pulse to the VCMA cells in the array of VCMA cells, wherein the stochastically tuned voltage pulse has a magnitude and duration that provides a 50%-50% switching distribution of the VCMA cells in the array of VCMA cells; and a bit output system for reading a state of each of the VCMA cells in the array of VCMA cells to provide a TRN or PUF.

公开(公告)号：US20210239903A1

公开(公告)日：2021-08-05

申请号：US16781324

申请日：2020-02-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/126 ,  G02B6/125 ,  G02B6/122 ,  G02B6/13

Abstract: Structures for a polarizer and methods of fabricating a structure for a polarizer. A first waveguide core has a first tapered section, a second tapered section, and a section positioned along a longitudinal axis between the first tapered section and the second tapered section. The first tapered section and the second tapered section each narrow in a direction along the longitudinal axis toward the section. A second waveguide core has a first terminating end, a second terminating end, and a section that is arranged between the first and second terminating ends. The section of the second waveguide core is positioned either over or below the section of the first waveguide core.

公开(公告)号：US11075268B2

公开(公告)日：2021-07-27

申请号：US16541600

申请日：2019-08-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haiting Wang ,  Sipeng Gu

IPC: H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

公开(公告)号：US20210217874A1

公开(公告)日：2021-07-15

申请号：US17214969

申请日：2021-03-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/737 ,  H01L21/762

Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the collector region.

公开(公告)号：US20210217849A1

公开(公告)日：2021-07-15

申请号：US16743589

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. ELLIS-MONAGHAN ,  John J. PEKARIK

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/78 ,  H01L21/74 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.

公开(公告)号：US11063140B2

公开(公告)日：2021-07-13

申请号：US16784683

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Herbert Ho ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L27/082

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

公开(公告)号：US11061315B2

公开(公告)日：2021-07-13

申请号：US16191589

申请日：2018-11-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jia Zeng ,  Guillaume Bouche ,  Lei Sun ,  Geng Han

IPC: H01L21/00 ,  G03F1/24 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/308

Abstract: Methods pattern a sacrificial material on an etch mask into mandrels using optical mask lithography, form a conformal material and a fill material on the mandrels, and planarize the fill material to the level of the conformal material. Such methods pattern the fill material into first mask features using extreme ultraviolet (EUV) lithography. These methods partially remove the conformal material to leave the conformal material on the sidewalls of the mandrels as second mask features. Spaces between the first mask features and the second mask features define an etching pattern. The spacing distance of the mandrels is larger than the spacing distance of the second mask features. Such methods transfer the etching pattern into the etch mask material, and subsequently transfer the etching pattern into an underlying layer. Openings in the underlying layer are filled with a conductor to form wiring in the etching pattern.

公开(公告)号：US11056591B2

公开(公告)日：2021-07-06

申请号：US16382184

申请日：2019-04-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jin Wallner ,  Heng Yang ,  Judson Robert Holt

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L21/84

Abstract: A method of forming a semiconductor device is provided, which includes providing gate structures over an active region and forming a hard mask segment on the active region positioned between a first gate structure and a second gate structure. Cavities are formed in the active region using the gate structures and the hard mask segment as masking features, wherein each cavity has a width substantially equal to a minimum gate-to-gate spacing of the semiconductor device. Epitaxial material is grown in the cavities to form substantially uniform epitaxial structures in the active region.

公开(公告)号：US11056533B1

公开(公告)日：2021-07-06

申请号：US16804952

申请日：2020-02-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Viorel Ontalus

IPC: H01L27/20 ,  H01L27/082 ,  H01L29/73

Abstract: One illustrative device disclosed herein includes a semiconductor substrate, a bipolar junction transistor (BJT) device that comprises a collector, a base and an emitter, at least one piezoelectric structure comprising a piezoelectric material positioned adjacent the BJT device, and at least first and second conductive contact structures that are conductively coupled to the piezoelectric structure.

公开(公告)号：US20210202722A1

公开(公告)日：2021-07-01

申请号：US16728172

申请日：2019-12-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Viorel C. Ontalus

IPC: H01L29/739 ,  H01L29/165 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L29/66

Abstract: Embodiments of the disclosure provide an insulated-gate bipolar transistor (IGBT), including: a substrate with a first type of doping; a drift region including a first semiconductor material and a second semiconductor material having dissimilar band gaps, the drift region having a second type of doping; and a base region with the first type of doping, wherein the drift region is disposed between the substrate and the base region; wherein a stoichiometry ratio of the first and second semiconductor materials of the drift region varies as a function of distance within the drift region to provide a built-in electric field via band gap modulation. The built-in electric field reduces a band gap barrier for minority charge carriers and increases a drift velocity of the minority charge carriers in the drift region, increasing a frequency response of the IGBT.