Method of noise estimation, corresponding device and computer program product

    公开(公告)号:US11387924B2

    公开(公告)日:2022-07-12

    申请号:US16858255

    申请日:2020-04-24

    Abstract: Noise in a communication channel is estimated by, in the absence of transmitted information packets, obtaining a plurality of sets of signal samples, and estimating noise power levels associated with the sets of signal samples and allotted to respective noise power classes. In the presence of at least one transmitted information packet, an information packet power level is estimated. A set of signal-to-noise ratios computed between the information packet power level and the noise power levels in the respective noise power classes are compared against a signal-to-noise threshold and partitioned into a first subset and a second subset of signal-to-noise ratios failing to exceed/exceeding, respectively, the threshold. One or more resulting impulsive noise parameters are computed as a function of impulsive noise parameters indicative of noise power levels in the signal-to-noise ratios in the first subset while disregarding impulsive noise parameters indicative of noise power levels in the second subset.

    Pulse width check circuit for laser diode pulse generator

    公开(公告)号:US11387625B2

    公开(公告)日:2022-07-12

    申请号:US16455063

    申请日:2019-06-27

    Abstract: A pulsed signal generator generates a pulsed signal having a pulse width intended to be equal to a given fraction of a pulse width of a reference clock. A reference current source outputs current having a reference magnitude, and a comparison current source outputs current having a magnitude that is a function of the reference magnitude and the given fraction. A comparison circuit compares a total current output by one of the reference current source and the comparison current source during pulses of the reference clock to a total current output by the other of the reference current source and the comparison current source during pulses of the pulsed signal equal in number to the pulses of the reference clock in order to determine whether the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock.

    HEMT TRANSISTOR WITH ADJUSTED GATE-SOURCE DISTANCE, AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20220216333A1

    公开(公告)日:2022-07-07

    申请号:US17703779

    申请日:2022-03-24

    Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, COMPONENT FOR USE THEREIN AND CORRESPONDING SEMICONDUCTOR DEVICE

    公开(公告)号:US20220199500A1

    公开(公告)日:2022-06-23

    申请号:US17550925

    申请日:2021-12-14

    Abstract: A leadframe includes a pattern of electrically-conductive formations with one or more sacrificial connection formations extending bridge-like between a pair of electrically-conductive formations. The sacrificial connection formation or formations are formed at one of the first surface and the second surface of the leadframe and have a thickness less than the leadframe thickness between the first surface and the second surface. A filling of electrically-insulating material is molded between the electrically-conductive formations of the leadframe, with electrically-insulating material molded between the connection formation(s) and the other surface of the leadframe. The sacrificial connection formation(s) counter deformation and displacement of parts during formation and pre-molding of the leadframe.

    System for controlling linear axis of a MEMS mirror

    公开(公告)号:US11368656B2

    公开(公告)日:2022-06-21

    申请号:US17356162

    申请日:2021-06-23

    Abstract: A device has memory and processing circuitry coupled to the memory. The processing circuitry generates a resonant axis drive signal to drive a Micro Electro Mechanical System (MEMS) mirror system at a resonance frequency, and generates a linear axis drive signal to drive the MEMS mirror system at a linear frequency corresponding to a video frame rate. Generating the linear axis drive signal includes generating, using interpolation, a current set of shape values based on a stored set of shape values and an indication of the video frame rate. The linear axis drive signal is generated using the current set of shape values.

    COMPACT LINE SCAN MEMS TIME OF FLIGHT SYSTEM WITH ACTUATED LENS

    公开(公告)号:US20220187591A1

    公开(公告)日:2022-06-16

    申请号:US17533890

    申请日:2021-11-23

    Abstract: Disclosed herein is an optical module including a substrate, with an optical detector, laser emitter, and support structure being carried by the substrate. An optical layer includes a fixed portion carried by the support structure, a movable portion affixed between opposite sides of the fixed portion by a spring structure, and a lens system carried by the movable portion. The movable portion has at least one opening defined therein across which the lens system extends, with at least one supporting portion extending across the at least one opening to support the lens system. The optical layer further includes a MEMS actuator for in-plane movement of the movable portion with respect to the fixed portion.

    HARDWARE ACCELERATOR DEVICE, CORRESPONDING SYSTEM AND METHOD OF OPERATION

    公开(公告)号:US20220180959A1

    公开(公告)日:2022-06-09

    申请号:US17453811

    申请日:2021-11-05

    Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

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