公开(公告)号：US20230015480A1

公开(公告)日：2023-01-19

申请号：US17391067

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chun-Hsien Lin ,  Yung-Chen Chiu ,  Chien-Liang Wu ,  Te-Wei Yeh

IPC: H01L27/112

Abstract: A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.

公开(公告)号：US20230014945A1

公开(公告)日：2023-01-19

申请号：US17945122

申请日：2022-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wen Huang ,  Shih-An Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L29/10

Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.

公开(公告)号：US20230013358A1

公开(公告)日：2023-01-19

申请号：US17951058

申请日：2022-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.

公开(公告)号：US11557654B2

公开(公告)日：2023-01-17

申请号：US17511586

申请日：2021-10-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/167 ,  H01L29/06

Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.

公开(公告)号：US11551955B2

公开(公告)日：2023-01-10

申请号：US16831739

申请日：2020-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Che Lai ,  Hua-Wei Peng ,  Chia-He Cheng ,  Ming-Tso Chen ,  Chao-Chi Lu ,  Hsin-Hsu Lin ,  Kuo-Tsai Lo ,  Kao-Hua Wu ,  Huan-Hsin Yeh

IPC: H01L21/67 ,  G05B19/418 ,  G06T7/00

Abstract: A substrate processing apparatus includes a process station for processing a substrate; a cassette station integrated with the process station; a substrate carriage equipped for transferring the substrate between said process station and the cassette station through a passage located at an interface between the process station and said cassette station; and a substrate scanner equipped at said interface between the process station and the cassette station for capturing surface image data during transportation of the substrate that passes through the passage.

公开(公告)号：US20230005833A1

公开(公告)日：2023-01-05

申请号：US17943215

申请日：2022-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/64 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L27/01

Abstract: A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.

公开(公告)号：US11545560B2

公开(公告)日：2023-01-03

申请号：US17160421

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

公开(公告)号：US11545484B2

公开(公告)日：2023-01-03

申请号：US17150960

申请日：2021-01-15

Applicant: United Microelectronics Corp.

Inventor： Jui-Fa Lu ,  Chien-Nan Lin ,  Ching-Hua Yeh

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49 ,  H01L23/528 ,  H01L29/66 ,  H01L23/532 ,  H01L49/02 ,  H01L23/522 ,  G06F30/39 ,  G06F30/392 ,  G06F119/18

Abstract: A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.

公开(公告)号：US20220415926A1

公开(公告)日：2022-12-29

申请号：US17383283

申请日：2021-07-22

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Chunyuan Qi ,  Xingxing Chen ,  Chien-Kee Pang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

公开(公告)号：US11538915B2

公开(公告)日：2022-12-27

申请号：US17163589

申请日：2021-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786

Abstract: A semiconductor device includes a substrate and a first transistor disposed on the substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. A material composition of the first vertical portion is identical to a material composition of each of the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions.