公开(公告)号：US5119263A

公开(公告)日：1992-06-02

申请号：US593427

申请日：1990-10-05

Applicant: Roberto Gariboldi ,  Alberto Gola

Inventor： Roberto Gariboldi ,  Alberto Gola

IPC: H02H9/04

CPC classification number: H02H9/047

Abstract: A negative overvoltage protection circuit for an insulated vertical PNP transistor the emitter whereof defines the input, the collector whereof defines the output and the base whereof is connected to an NPN driving transistor. In order to maximally extend the negative overvoltage which can be applied to the output, the protection circuit comprises an output voltage sensor, a voltage reference, a comparator which is connected in input to the voltage reference and to the sensor and generates in output an activation signal when the output voltage of the PNP transistor becomes smaller than the reference, a switch which is controlled by the comparator to switch off the NPN driving transistor upon the reception of the activation signal and a low-impedance circuit which is connected between the emitter and the base of the insulated vertical PNP transistor and is activated by the activation signal, in a manner suitable for bringing the insulated vertical PNP transistor practically to BV.sub.CBO.

公开(公告)号：US5117269A

公开(公告)日：1992-05-26

申请号：US487480

申请日：1990-03-02

Applicant: Orio Bellezza ,  Massimo Melanotte

Inventor： Orio Bellezza ,  Massimo Melanotte

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11517 ,  H01L27/115

Abstract: In order to obtain an EPROM memory array with high compactness and the possibility of asymmetrically doping the channel, an array is proposed which comprises a substrate having a first conductivity type, first and second bit lines having the opposite conductivity type and extending parallel and mutually alternated in the substrate, a plurality of thick insulating material regions extending at least partially in the substrate above and parallel to the first bit lines, a plurality of floating gate regions extending above the substrate perpendicular to and between adjacent pairs of bit lines, a plurality of word lines extending perpendicular to the bit lines and above, but electrically insulated from, the floating gate regions, wherein the second bit lines extend up to the surface of the substrate and define unburied bit lines to the side whereof it is possible to provide enriched channel regions. The unburied bit lines can furthermore be subjected to a siliciding process to reduce series resistance.

公开(公告)号：US5113305A

公开(公告)日：1992-05-12

申请号：US511408

申请日：1990-04-19

Applicant: Salvatore Raciti ,  Sergio Palara

Inventor： Salvatore Raciti ,  Sergio Palara

IPC: H01L29/73 ,  H01L21/331 ,  H01L27/02 ,  H01L27/06 ,  H01L29/732 ,  H03K17/082

CPC classification number: H01L27/0248 ,  H03K17/0826

Abstract: The protection device ocmprises automatic commutating means interposed between the base of a transistor to be protected and the collector of a power device to cause a flow of current having a low voltage drop between the base and the collector when the collector voltage falls below a predetermined value.

公开(公告)号：US5113240A

公开(公告)日：1992-05-12

申请号：US656386

申请日：1991-02-19

Applicant: Pieramedeo Bozzini ,  Giuseppe Marchisi

Inventor： Pieramedeo Bozzini ,  Giuseppe Marchisi

IPC: H01L23/28 ,  H01L23/495 ,  H01L23/50

CPC classification number: H01L23/49541 ,  H01L23/49503 ,  H01L23/49568 ,  H01L2924/0002

Abstract: An improved leadframe for packages of integrated power devices which, by virtue of its configuration, allows to press the dissipator on the bottom of the shell during the molding of the plastic case, without the dissipator having exposed portions of its inner face (which is in contact with the chip). In order to achieve this, the leadframe according to the invention comprises a monolithic body which defines a perimetric frame, the leads and the dissipator. The dissipator extends in a depressed plane with respect to the frame and is connected to the frame and to the leads in at least three step-like points which are mutually spaced and non-aligned. During the molding of the plastic case, a pressure is exerted on the frame and is transmitted to the dissipator by the three step-like points, so that the dissipator is effectively pressed flat against the bottom of the mold without using pushers which pass through the plastic case.

公开(公告)号：US5107389A

公开(公告)日：1992-04-21

申请号：US523954

申请日：1990-05-15

Applicant: Edoardo Botti ,  Fabrizio Stefani

Inventor： Edoardo Botti ,  Fabrizio Stefani

IPC: H03F1/52

CPC classification number: H03F1/52 ,  H03F2200/447

Abstract: A circuit for limiting temperature without distortion in audio power amplifiers, comprising a temperature sensor for sensing the temperature in an audio power amplifier, and a variable-gain amplifier connected ahead of the audio power amplifier circuit and having a gain control input connected to the temperature sensor to vary the input signal of the audio amplifier in a linear manner. A linear limitation of the power, and therefore of the temperature, is thus obtained in the audio amplifier without introducing distortion.

公开(公告)号：US5105324A

公开(公告)日：1992-04-14

申请号：US518018

申请日：1990-05-02

Applicant: Bruno Murari ,  Claudio Diazzi ,  Klaus Rischmuller

Inventor： Bruno Murari ,  Claudio Diazzi ,  Klaus Rischmuller

IPC: H01L23/62 ,  G05F1/10 ,  H02H3/10 ,  H02H3/22 ,  H02H9/04

CPC classification number: H02H9/04

Abstract: A series of Zener diodes (25) and an electronic power switch, such as an IGBT (18), are connected across a power supply. A circuit including a resistor (20) in series on the electronic switch, a threshold device (36, 38) connected to the resistor and a ramp generator with multiplier (40, 42, 44, 46, FIG. 2) or a thermal sensor (50, 44, 46 FIG. 3) detect the energy level dissipated in the electronic power switch when a transient occurs when the level exceeds a present value, the circuit supplies an output signal to a monostable circuit (26, 28, 48) to drive the electronic power switch with low resistance conditions for a preset time starting from the occurrence of the output signal. Another threshold device, connected to a resistor (30, 32), preferably senses the instantaneous power dissipated in the electronic switch to control the monostable circuit when the instantaneous power is higher than a preset threshold.

公开(公告)号：US5083182A

公开(公告)日：1992-01-21

申请号：US425981

申请日：1989-10-24

Applicant: David Ballaro' ,  Alfonso Patti ,  Giuseppe Ferla ,  Ferruccio Frisina

Inventor： David Ballaro' ,  Alfonso Patti ,  Giuseppe Ferla ,  Ferruccio Frisina

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/732

CPC classification number: H01L27/0825

Abstract: The emitter region of a speed-up transistor is created in a base of a final transistor of a Darlington device and has a relatively low dopant concentration and small thickness.

公开(公告)号：US5077489A

公开(公告)日：1991-12-31

申请号：US606038

申请日：1990-10-30

Applicant: Alberto Gola ,  Angelo Alzati ,  Aldo Novelli

Inventor： Alberto Gola ,  Angelo Alzati ,  Aldo Novelli

IPC: H03K5/08 ,  H03F3/45 ,  H03K5/24

CPC classification number: H03F3/4508 ,  H03F3/45076 ,  H03F3/45179 ,  H03F3/45286 ,  H03F3/45291 ,  H03K5/2445 ,  H03F2203/45028 ,  H03F2203/45144 ,  H03F2203/45188 ,  H03F2203/45304 ,  H03F2203/45612

Abstract: An electronic comparator circuit having a high speed during switch phase and combining the advantages of bipolar technology with those of CMOS technology. The circuit consists of a differential stage input circuit having a differential pair of bipolar transistors forming its outputs. The output stage contains a pair of MOS transistors having gate electrodes in common. The pair of MOS transistors is connected on one side to the outputs of the input portion and on the other side to a positive supply pole via a current mirror circuit. The output contains another pair of MOS transistors with gate electrodes in common connected between the outputs of the input portion and ground. The drain electrode of the first pair of MOS transistors forms the output for the comparator.

公开(公告)号：US5045910A

公开(公告)日：1991-09-03

申请号：US381340

申请日：1989-07-17

Applicant: Flavio Villa

Inventor： Flavio Villa

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/732 ,  H03F1/30 ,  H03F1/52 ,  H03F3/04 ,  H03F3/343 ,  H03F3/347 ,  H03F3/68 ,  H03K17/00 ,  H03K17/08 ,  H03K17/0812 ,  H03K17/12

CPC classification number: H03K17/12 ,  H03K17/08126 ,  H03K2017/0806 ,  H03K2217/0036

Abstract: An integrated power transistor with reduced sensitivity to thermal stresses and improved resistance to direct secondary breakdown, comprising a plurality of transistors having their emitter regions connected so as to define a common emitter terminal, their collector regions connected so as to define a common collector region, and the same plurality of diodes connected to the respective transistors to form therewith a current mirror circuit, each base of the transistors being connected to the first terminal of a corresponding resistor, the second terminal of the corresponding resistors being connected to a common base.

公开(公告)号：US5041895A

公开(公告)日：1991-08-20

申请号：US535774

申请日：1990-06-08

Applicant: Claudio Contiero ,  Paola Galbiati ,  Luica Zullino

Inventor： Claudio Contiero ,  Paola Galbiati ,  Luica Zullino

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/092 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L27/0623

Abstract: Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called "smart power" type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any "level shifting" stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.