公开(公告)号：US08334188B2

公开(公告)日：2012-12-18

申请号：US12791553

申请日：2010-06-01

Applicant: Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

Inventor： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

IPC: H01L21/76

CPC classification number: H01L21/76283 ,  H01L21/3003 ,  H01L21/3247 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0649 ,  Y10S438/967

Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.

Abstract translation: 一种制造SOI晶片的方法，包括以下步骤：在半导体材料的晶片中形成限定半导体材料结构的空腔; 通过热过程稀释结构; 并完全氧化结构。

公开(公告)号：US20080036030A1

公开(公告)日：2008-02-14

申请号：US11904745

申请日：2007-09-28

Applicant: Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

Inventor： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

IPC: H01L29/00 ,  H01L21/764

CPC classification number: H01L21/76283 ,  H01L21/3003 ,  H01L21/3247 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0649 ,  Y10S438/967

Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.

Abstract translation: 一种制造SOI晶片的方法，包括以下步骤：在半导体材料的晶片中形成限定半导体材料结构的空腔; 通过热过程稀释结构; 并完全氧化结构。

公开(公告)号：US20070126071A1

公开(公告)日：2007-06-07

申请号：US11541376

申请日：2006-09-27

Applicant: Pietro Corona ,  Flavio Villa ,  Gabriele Barlocchi

Inventor： Pietro Corona ,  Flavio Villa ,  Gabriele Barlocchi

IPC: H01L29/84 ,  H01L21/00

CPC classification number: B81C1/00158 ,  B81B2201/025 ,  B81B2203/0109 ,  B81B2203/0315

Abstract: A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region of the monolithic body, said surface region having a first thickness; carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body towards the surface region and thus form a suspended structure above the buried cavity, the suspended structure having a second thickness greater than the first thickness. The thickening thermal treatment is an annealing treatment.

Abstract translation: 制造半导体材料的悬浮结构的方法设想的步骤：提供具有正面的半导体材料的整体; 在所述整体式主体内形成掩埋空腔，所述掩埋腔在所述前表面的一定距离处延伸并且与所述前表面一起界定所述整体式主体的表面区域，所述表面区域具有第一厚度; 进行增稠热处理，使得整体式体的半导体材料朝向表面区域移动，从而在掩埋空腔之上形成悬浮结构，该悬浮结构的第二厚度大于第一厚度。 增稠热处理是退火处理。

公开(公告)号：US20060260408A1

公开(公告)日：2006-11-23

申请号：US11417683

申请日：2006-05-04

Applicant: Flavio Villa ,  Pietro Corona ,  Gabriele Barlocchi ,  Lorenzo Baldo

Inventor： Flavio Villa ,  Pietro Corona ,  Gabriele Barlocchi ,  Lorenzo Baldo

IPC: B05D5/12 ,  G01L7/08

CPC classification number: G01L9/0045 ,  G01L13/025

Abstract: A process for manufacturing an integrated differential pressure sensor includes forming, in a monolithic body of semiconductor material having a first face and a second face, a cavity extending at a distance from the first face and delimiting therewith a flexible membrane, forming an access passage in fluid communication with the cavity, and forming, in the flexible membrane, at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and delimits, together with the second face, a portion of the monolithic body. In order to form the access passage, the monolithic body is etched so as to form an access trench extending through it.

Abstract translation: 一种用于制造集成差压传感器的方法，包括在具有第一面和第二面的半导体材料的整体中形成一个与第一面相距一定距离的空腔，并将其限定在柔性膜上，形成入口通道 与空腔流体连通，以及在柔性膜中形成至少一个换能元件，其构造成将柔性膜的变形转换为电信号。 空腔形成在距第二面一定距离处的位置，并与第二面一起界定整体式的一部分。 为了形成进入通道，对整体式主体进行蚀刻以便形成延伸通过其的通道沟槽。

公开(公告)号：US20050142597A1

公开(公告)日：2005-06-30

申请号：US10997235

申请日：2004-11-24

Applicant: Ubaldo Mastromatteo ,  Flavio Villa ,  Gabriele Barlocchi

Inventor： Ubaldo Mastromatteo ,  Flavio Villa ,  Gabriele Barlocchi

IPC: B01L3/00 ,  B01L7/00 ,  B81B3/00 ,  C12M1/34 ,  C12Q1/68 ,  H01L21/00

CPC classification number: B01L3/502715 ,  B01L3/5025 ,  B01L3/502707 ,  B01L7/52 ,  B01L2200/027 ,  B01L2200/12 ,  B01L2300/044 ,  B01L2300/0816 ,  B01L2300/1827

Abstract: The microreactor is formed by a sandwich including a first body, an intermediate sealing layer and a second body. A buried channel extends in the first body and communicates with the surface of the first body through a first and a second apertures. A first and a second reservoirs are formed in the second body and are at least partially aligned with the first and second apertures. The sealing layer separates the first aperture from the first reservoir and the second aperture from the second reservoir, thereby avoiding contamination of liquids contained in the buried channel from the outside and from any adjacent buried channels. The sealing layer is perforated during use of the device, but a resilient plug can be used to reseal the device.

Abstract translation: 微反应器由包括第一主体，中间密封层和第二主体的夹层形成。 掩埋通道在第一主体中延伸并且通过第一和第二孔与第一主体的表面连通。 第一和第二储存器形成在第二主体中并且至少部分地与第一和第二孔对准。 密封层将第一孔与第一储存器和第二孔分隔开来自第二储存器，从而避免了从外部和任何相邻的埋入通道污染包含在掩埋通道中的液体。 在使用该装置期间密封层是穿孔的，但是可以使用弹性塞来重新密封装置。

公开(公告)号：US5756387A

公开(公告)日：1998-05-26

申请号：US581493

申请日：1995-12-29

Applicant: Flavio Villa ,  Paolo Ferrari

Inventor： Flavio Villa ,  Paolo Ferrari

IPC: H01L21/329 ,  H01L29/866 ,  H01L21/8222

CPC classification number: H01L29/66106 ,  H01L29/866 ,  Y10S438/912 ,  Y10S438/983

Abstract: Zener diode with high stability in time and low noise for integrated circuits and provided in an epitaxial pocket insulated from the rest of a type N epitaxial layer grown on a substrate of type P semiconductor material. In said pocket are included a type N+ cathode region and a type P anode region enclosing it. The cathode region has a peripheral part surrounding a central part extending in the anode region less deeply than the peripheral part.

Abstract translation: 在集成电路的时间上具有高稳定性和低噪声的齐纳二极管，并且提供在与类型P半导体材料的衬底上生长的N型外延层的其余部分绝缘的外延袋中。 在所述口袋中包括N +型阴极区和包围它的P型阳极区。 阴极区域具有围绕在阳极区域延伸的中心部分的周边部分不比周边部分深。

公开(公告)号：US5595921A

公开(公告)日：1997-01-21

申请号：US459052

申请日：1995-06-02

Applicant: Flavio Villa ,  Enrico M. A. Ravanelli

Inventor： Flavio Villa ,  Enrico M. A. Ravanelli

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/7816 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/0878 ,  Y10S148/126

Abstract: The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.

Abstract translation: 集成在具有相反导电性的衬底上生长并且包括形成在所述外延层中的漏极区的第一类型导电体的外延层中的横向晶体管的击穿特性显着改善，而不会重复进行物理参数的临界调整 通过形成具有相同类型的衬底的导电性的掩埋区域和在位于晶体管的漏极区域下方的区域中在外延层和衬底之间的界面处稍微更高的掺杂水平的一体结构。

公开(公告)号：US4979008A

公开(公告)日：1990-12-18

申请号：US298651

申请日：1989-01-18

Applicant: Marco Siligoni ,  Flavio Villa

Inventor： Marco Siligoni ,  Flavio Villa

IPC: H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L29/7302 ,  H01L29/0826 ,  H01L29/7322 ,  Y10S257/914 ,  Y10S257/918

Abstract: A vertical, isolated-collector transistor of the pnp type comprises an island doped similarly to the collector region and formed in the surface epitaxial layer of the transistor between that collector region and one of the isolation zones. That island extends in depth to penetrate a similarly doped intermediate region and short out the epitaxial layer included between the isolating layer and the collector region so as to suppress the effects of active parasitic junction components by holding a transistor and a silicon-controlled rectifier of parasitic types, as nesting within the structure of the vertical pnp transistor, in a cut-off state.

公开(公告)号：US4821136A

公开(公告)日：1989-04-11

申请号：US99356

申请日：1987-09-21

Applicant: Bruno Murari ,  Flavio Villa

Inventor： Bruno Murari ,  Flavio Villa

IPC: H01L29/73 ,  H01L21/331 ,  H02H7/20 ,  H02H9/02 ,  H03F1/42 ,  H03F1/52 ,  H03K17/082

CPC classification number: H02H7/205 ,  H02H9/02 ,  H03K17/0826

Abstract: A power transistor with self-protection against direct secondary breakdown comprises a plurality of elementary transistors having their emitter terminals mutually connected and forming a common emitter terminal, collector terminals also mutually connected and forming a common collector terminal, and base terminals connected to at least one current source. Switches are furthermore provided selectively associated with some of the elementary transistors, preferably with one elementary transistor every two, and allowing operation of the associated elementary transistors in the saturation operating region and switching off the associated elementary transistors during high-voltage operation.

Abstract translation: 具有防止直接二次击穿的自我保护的功率晶体管包括多个基本晶体管，其发射极端子相互连接并形成共同的发射极端子，集电极端子也相互连接并形成公共集电极端子，基极端子连接到至少一个 当前来源。 此外，开关还被提供选择性地与一些基本晶体管相关联，优选地每两个一个基本晶体管，并且允许在饱和工作区域中相关联的基本晶体管的操作，并且在高电压操作期间关断相关联的基本晶体管。

公开(公告)号：US4663647A

公开(公告)日：1987-05-05

申请号：US779091

申请日：1985-09-23

Applicant: Franco Bertotti ,  Paolo Ferrari ,  Luigi Silvestri ,  Flavio Villa

Inventor： Franco Bertotti ,  Paolo Ferrari ,  Luigi Silvestri ,  Flavio Villa

IPC: H01L27/04 ,  H01L21/761 ,  H01L21/822 ,  H01L29/8605 ,  H01L27/02 ,  H01C1/012

CPC classification number: H01L29/8605 ,  H01L21/761

Abstract: A buried-resistance semiconductor device is constructed by forming a P-type monocrystalline silicon substrate on which an epitaxial layer of silicon doped with type N impurities is grown, a portion of the epitaxial layer being insulated by a P-type insulating region extending from the substrate to the surface of the epitaxial layer. Two suitably-spaced terminals are secured to the surface of the epitaxial layer in the area bounded by the insulating region. Two separation regions extending into the surface layer are formed in the part of the epitaxial layer between the terminals, and a buried region extends from the substrate between the separation regions without being in contact with them. The three regions are of P-type material, and have an elongated shape and are bounded at the ends by the insulating region.

Abstract translation: 掩埋电阻半导体器件通过形成P型单晶硅衬底而构成，其上生长掺杂有N型杂质的硅的外延层，外延层的一部分由从P型绝缘区延伸的P型绝缘区绝缘 衬底到外延层的表面。 两个适当间隔的端子在由绝缘区域限定的区域中固定到外延层的表面。 延伸到表面层的两个分离区域形成在端子之间的外延层的部分中，并且掩埋区域在分离区域之间从衬底延伸而不与它们接触。 这三个区域是P型材料，并且具有细长形状并且在末端被绝缘区限定。