公开(公告)号：US06815268B1

公开(公告)日：2004-11-09

申请号：US10301732

申请日：2002-11-22

Applicant: Bin Yu ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy

Inventor： Bin Yu ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method of forming a gate in a FinFET device includes forming a fin on an insulating layer, forming source/drain regions and forming a gate oxide on the fin. The method also includes depositing a gate material over the insulating layer and the fin, depositing a barrier layer over the gate material and depositing a bottom anti-reflective coating (BARC) layer over the barrier layer. The method further includes forming a gate mask over the BARC layer, etching the BARC layer, where the etching terminates on the barrier layer, and etching the gate material to form the gate.

Abstract translation: 在FinFET器件中形成栅极的方法包括在绝缘层上形成鳍片，形成源极/漏极区域并在鳍片上形成栅极氧化物。 该方法还包括在绝缘层和鳍上沉积栅极材料，在栅极材料上沉积阻挡层并在阻挡层上沉积底部抗反射涂层（BARC）层。 该方法还包括在BARC层上形成栅极掩模，蚀刻BARC层，其中蚀刻在阻挡层上终止，并蚀刻栅极材料以形成栅极。

公开(公告)号：USRE38608E1

公开(公告)日：2004-10-05

申请号：US10052843

申请日：2002-01-17

Applicant: Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

Inventor： Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

IPC: H01L2900

CPC classification number: H01L29/8618 ,  H01L29/866

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p− region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm−3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p− layer should be between about 0.5E14 cm−3 and about 1.OE17 cm−3. The junction depth of the fourth (n+) region should be greater than about 0.3 &mgr;m. The thickness of the third (p+) region should be between about 0.3 &mgr;m and about 2.0 &mgr;m, and the thickness of the second (p−) region should be between about 0.5 &mgr;m and about 5.0 &mgr;m.

公开(公告)号：US06787852B1

公开(公告)日：2004-09-07

申请号：US10278420

申请日：2002-10-23

Applicant: Bin Yu ,  Ralf van Bentum

Inventor： Bin Yu ,  Ralf van Bentum

IPC: H01L2701

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes a substrate having a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer. The active layer has an active region defined by isolation regions, the active region having a source and a drain with a body disposed therebetween. The source and the drain have a selectively grown silicon-germanium region disposed under an upper layer of selectively grown silicon. The silicon-geranium regions form heterojunction portions respectively along the source/body junction and the drain/body junction.

Abstract translation: 绝缘体上半导体（SOI）器件。 SOI器件包括其上设置有掩埋氧化物层的衬底和设置在掩埋氧化物层上的有源层。 有源层具有由隔离区域限定的有源区域，有源区域具有源极和漏极，其间设置有主体。 源极和漏极具有选择性地生长的硅 - 锗区域，其设置在选择性生长的硅的上层下方。 硅锗天线分别沿着源极/主体结和漏极/主体结形成异质结部分。

公开(公告)号：US06784101B1

公开(公告)日：2004-08-31

申请号：US10146029

申请日：2002-05-16

Applicant: Bin Yu ,  David Wu

Inventor： Bin Yu ,  David Wu

IPC: H01L2144

CPC classification number: H01L21/022 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/28194 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/1054 ,  H01L29/517

Abstract: A semiconductor device is formed by providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice therein, forming a thin buffer/interfacial layer of a low-k dielectric material on the upper surface of the semiconductor substrate, and forming a layer of a high-k dielectric material on the thin buffer/interfacial layer of a low-k dielectric material. Embodiments include forming the thin buffer/interfacial layer and high-k layer at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of the strained lattice semiconductor layer.

Abstract translation: 半导体器件通过在其上表面设置包含应变晶格半导体层并在其中具有预选量的晶格的半导体衬底形成，在上表面上形成低k介电材料的薄缓冲/界面层 并且在低k电介质材料的薄缓冲层/界面层上形成高k电介质材料层。 实施例包括在足以实现相应电介质层的形成的最小温度下形成薄缓冲层/界面层和高k层，而不会引起应变晶格半导体层的应变弛豫或至少最小化应变弛豫。

公开(公告)号：US06774436B1

公开(公告)日：2004-08-10

申请号：US09900400

申请日：2001-07-05

Applicant: Bin Yu ,  Ralf van Bentum

Inventor： Bin Yu ,  Ralf van Bentum

IPC: H01L310392

CPC classification number: H01L29/66772 ,  H01L29/78612 ,  H01L29/78624

Abstract: A semiconductor-on-insulator (SOI) device. The SOi device includes a substrate, an insulator layer disposed on the substrate and an active region disposed on the insulator layer. The active region includes a source, a drain, and a body disposed therebetween. The source and body form an abrupt or hyperabrupt source/body junction. A gate is disposed on the body to operatively form a transistor. An implanted region forms an interface between the body and the drain, the implanted region formed by tilted atom implantation in a direction towards the active region and under the gate from an angle tilted towards the drain with respect to vertical, the implanted region resulting in the formation of a graded drain/body junction. Also disclosed is a method of fabricating the SOI device.

Abstract translation: 绝缘体上半导体（SOI）器件。 SOi器件包括衬底，设置在衬底上的绝缘体层和设置在绝缘体层上的有源区。 有源区域包括源极，漏极和设置在它们之间的主体。 来源和身体形成突然或超破坏的源/体结。 栅极设置在主体上以可操作地形成晶体管。 植入区域在主体和漏极之间形成界面，通过倾斜的原子注入在朝向有源区域的方向上形成的注入区域和从栅极相对于垂直方向朝向漏极倾斜的角度形成注入区域， 形成分级排水/身体结。 还公开了一种制造SOI器件的方法。

公开(公告)号：US06717212B2

公开(公告)日：2004-04-06

申请号：US09879724

申请日：2001-06-12

Applicant: Dong-Hyuk Ju ,  William George En ,  Srinath Krishnan ,  Concetta E. Riccobene ,  Zoran Krivokapic ,  Judy Xilin An ,  Bin Yu

Inventor： Dong-Hyuk Ju ,  William George En ,  Srinath Krishnan ,  Concetta E. Riccobene ,  Zoran Krivokapic ,  Judy Xilin An ,  Bin Yu

IPC: H01L31392

CPC classification number: H01L21/76254 ,  H01L21/187 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78612

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Abstract translation: 一种用于制造绝缘体半导体（SOI）结构的装置和方法，其具有设置在半导体衬底和半导体层之间的具有泄漏的导热材料（LTCIM）层。

公开(公告)号：US06716690B1

公开(公告)日：2004-04-06

申请号：US10385692

申请日：2003-03-12

Applicant: Haihong Wang ,  Judy Xilin An ,  Bin Yu

Inventor： Haihong Wang ,  Judy Xilin An ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L29/458 ,  H01L29/66795 ,  Y10S438/914

Abstract: Multiple dopant implantations are performed on a FinFET device to thereby distribute the dopant in a substantially uniform manner along a vertical depth of the FinFET in the source/drain junction. Each of the multiple implantations may be performed at different tilt angles.

Abstract translation: 在FinFET器件上执行多个掺杂剂注入，从而沿着源极/漏极结中的FinFET的垂直深度以大致均匀的方式分布掺杂剂。 多个注入中的每一个可以以不同的倾斜角执行。

公开(公告)号：US06709982B1

公开(公告)日：2004-03-23

申请号：US10303702

申请日：2002-11-26

Applicant: Matthew S. Buynoski ,  Judy Xilin An ,  Haihong Wang ,  Bin Yu

Inventor： Matthew S. Buynoski ,  Judy Xilin An ,  Haihong Wang ,  Bin Yu

IPC: H01L21311

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L29/66795

Abstract: A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.

Abstract translation: 一种在半导体器件中形成一组结构的方法包括在基底上形成导电层，其中导电层包括导电材料，并在导电层上形成氧化物层。 该方法还包括蚀刻氧化物层中的至少一个开口，用导电材料填充至少一个开口，蚀刻导电材料以在至少一个开口的侧壁上形成间隔物，并且去除氧化物层和一部分 导电层形成一组结构。

公开(公告)号：US06709935B1

公开(公告)日：2004-03-23

申请号：US09817580

申请日：2001-03-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L29/1054 ,  H01L29/66545

Abstract: A method of forming a specialized channel region removes a sacrificial gate material and provides a semiconductor implant though the recess associated with the remove sacrificial gate material. The process can be utilized to form a silicon germanium layer in the channel region having a sharp profile in the vertical direction. Further, the silicon germanium layer can be ultra-thin. The silicon germanium channel region has increased charge mobility with respect to conventional channel regions.

Abstract translation: 形成专用沟道区的方法去除牺牲栅极材料并通过与去除的牺牲栅极材料相关联的凹槽来提供半导体注入。 该方法可用于在垂直方向具有锐利轮廓的通道区域中形成硅锗层。 此外，硅锗层可以是超薄的。 硅锗沟道区相对于常规沟道区具有增加的电荷迁移率。

公开(公告)号：US06703281B1

公开(公告)日：2004-03-09

申请号：US10274038

申请日：2002-10-21

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659

Abstract: MOSFETs are fabricated with accurately defined, high and uniformly concentrated source/drain regions and extensions employing plural, sequential pre-amorphizing, implanting and laser thermal annealing steps with intervening spacer removal. Embodiments include forming sidewall spacers on a gate electrode, sequentially pre-amorphizing, ion implanting and laser thermal annealing to form deep source/drain regions, removing the sidewall spacers, and then sequentially pre-amorphizing, ion implanting and laser thermal annealing to form shallow source/drain extensions.

Abstract translation: 使用精确定义的高均匀浓度的源极/漏极区域和采用多个连续的前非晶化，注入和激光热退火步骤的间隔来制造MOSFET，并且间隔物移除。 实施例包括在栅电极上形成侧壁间隔物，顺序地预非晶化，离子注入和激光热退火以形成深源极/漏极区域，去除侧壁间隔物，然后依次预非晶化，离子注入和激光热退火以形成浅的 源/漏扩展。