公开(公告)号：US11145719B2

公开(公告)日：2021-10-12

申请号：US16396609

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78 ,  H01L23/535 ,  H01L23/525 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a first and a second gate stacks disposed over a substrate, having spacers along sidewalls, respectively. The device also includes a source/drain (S/D) feature, a capping layer disposed along upper portions of the spacers, respectively and a dielectric layer along lower portions of the spacers, respectively. The dielectric layer physically contacts the capping layer and a top surface of the dielectric layer is above a top surface of the S/D feature. The device also includes a contact disposed over the S/D feature interfacing the capping layer and dielectric layer.

公开(公告)号：US20210257310A1

公开(公告)日：2021-08-19

申请号：US16869894

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

IPC: H01L23/544 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238

Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.

公开(公告)号：US11075282B2

公开(公告)日：2021-07-27

申请号：US16689033

申请日：2019-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-An Liu ,  Chan-Lon Yang ,  Bharath Kumar Pulicherla ,  Zhi-Qiang Wu ,  Chung-Cheng Wu ,  Chih-Han Lin ,  Gwan-Sin Chang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

Abstract: A method includes forming a gate layer over a semiconductor fin; forming a patterned mask over the gate layer; performing a first etching process to pattern the gate layer using the patterned mask as an etch mask, the patterned gate layer comprising a first gate extending across the semiconductor fin; depositing, by using an directional ion beam, a protection layer to wrap around a top surface, a first sidewall and a second sidewall of the first gate, the protection layer extending along the first and second sidewalls of the first gate towards a bottom surface of the first gate without extending to the bottom surface of the first gate on the second sidewall of the first gate; and after depositing the protection layer, performing a second etching process to a portion of the second sidewall of the first gate exposed by the protection layer.

公开(公告)号：US20210217750A1

公开(公告)日：2021-07-15

申请号：US17194835

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.

公开(公告)号：US20210134982A1

公开(公告)日：2021-05-06

申请号：US16822609

申请日：2020-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.

公开(公告)号：US10985055B2

公开(公告)日：2021-04-20

申请号：US14984568

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/485

Abstract: An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure, a conductive structure and an anti-adhesion layer. The liner layer is present on the non-insulator structure and has an opening therein. The dielectric structure is present on the liner layer. The dielectric structure includes a via opening therein. The via opening has a sidewall. The conductive structure is present in the via opening of the dielectric structure and electrically connected to the non-insulator structure through the opening of the liner layer. The anti-adhesion layer is present between the sidewall of the via opening of the dielectric structure and the conductive structure.

公开(公告)号：US20210074591A1

公开(公告)日：2021-03-11

申请号：US17099613

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065

Abstract: A method includes providing a structure having a substrate and a fin protruding from the substrate, forming a gate stack layer over the fin, and patterning the gate stack layer in forming a gate stack. The patterning of the gate stack layer simultaneously forms a passivation layer on sidewall surfaces of the gate stack. The method also includes removing a bottom portion of the passivation layer, thereby exposing a bottom portion of the gate stack, while a top portion of the passivation layer remains. The method further includes laterally etching the bottom portion of the gate stack, thereby shrinking a width of the bottom portion of the gate stack.

公开(公告)号：US20210036148A1

公开(公告)日：2021-02-04

申请号：US17074532

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/8234 ,  H01L21/67

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

公开(公告)号：US10861977B2

公开(公告)日：2020-12-08

申请号：US16714607

申请日：2019-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/66

Abstract: A device includes a semiconductive substrate, a stop layer over the semiconductive substrate, first and second semiconductive fins over the stop layer, a fin isolation structure between the first and second semiconductive fins, and a spacer at least partially extending along a sidewall of the fin isolation structure. A bottom of the fin isolation structure is lower than a top of the stop layer.

公开(公告)号：US10811412B2

公开(公告)日：2020-10-20

申请号：US16524142

申请日：2019-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.