公开(公告)号：US5034706A

公开(公告)日：1991-07-23

申请号：US559799

申请日：1990-07-30

Applicant: Giorgio Betti ,  Maurizio Zuffada

Inventor： Giorgio Betti ,  Maurizio Zuffada

IPC: H03L7/099 ,  H03B5/12

CPC classification number: H03B5/1231 ,  H03B5/1209 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1243 ,  H03B2200/0062

Abstract: A voltage-controlled variable oscillator, in particular for phase-lock loops, comprising a differential stage formed by a pair of transistors and collectors whereof define the output terminals between which an external resonating circuit is connected, a voltage generator which is connected between the two output terminals and is suitable for generating a voltage which is proportional to the terminal voltage which exists across the resonating circuit, and a pair of capacitors connected between a respective output terminal and the voltage source.

公开(公告)号：US5012130A

公开(公告)日：1991-04-30

申请号：US394226

申请日：1989-08-15

Applicant: Paolo Menegoli ,  Marco Morelli ,  Francesco Tricoli

Inventor： Paolo Menegoli ,  Marco Morelli ,  Francesco Tricoli

IPC: H03K3/286 ,  H03K3/289 ,  H03K23/00

CPC classification number: H03K3/289

Abstract: A pair of control transistors and a pair of storage transistors have their collectors coupled to a current source. The emitters of the storage transistors are grounded and the emitters of the control transistors are coupled to the bases of the storage transistors. The control transistor collector and base electrodes are cross-coupled, and the storage transistor collector and base electrodes are also cross-coupled. The emitter of each control transistor is connected to the collector of the associative storage transistor through a respective resistor. Two diodes in series connect the collectors of the control transistor, and a command transistor having a grounded emitter electrode, drives the common node of the diodes.

公开(公告)号：US5005060A

公开(公告)日：1991-04-02

申请号：US326809

申请日：1989-03-21

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/115 ,  H01L29/7885

Abstract: The memory matrix comprises parallel and alternating source and drain lines, floating gate areas placed between the source and drain lines and control gate lines parallel to each other and perpendicular to the source and drain lines superimposed on the floating gate areas. The floating gate areas are arranged in rows parallel to the source and drain lines in positions longitudinally staggered in relation to those of the adjacent row in such a manner that the floating gate areas of one row underlie a first plurality of control gate lines and the floating gate areas of the adjacent row underlie a second plurality alternating with the first of the control gate lines. The floating gate areas together with the adjacent source and drain lines and with the superimposed control gate lines define respective EPROM cells arranged in a staggered manner in the memory matrix.

公开(公告)号：US4997782A

公开(公告)日：1991-03-05

申请号：US386189

申请日：1989-07-28

Applicant: Carlo Bergonzoni

Inventor： Carlo Bergonzoni

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/6659 ,  H01L21/823814

Abstract: By means of a single additional masking step lightly doped drain regions are formed in p-channel and n-channel CMOS transistors. The improved CMOS process comprises, after having formed the gates within the active areas and before forming spacers along the sides of the gate, implanting over the entire unmasked surface of the front of the device formed on a silicon substrate of a first polarity a quantity of dopant of a second polarity, identical to the well region polarity, sufficient to form lightly doped drain regions in transistors with a channel of said second polarity, forming a first time the mask for implantations of said first polarity and implanting the relative dopant in a dose sufficient to compensate and invert completely the previous implantation and to form lightly doped drain regions in transistors with a channel of said first polarity formed within the well region. The fabrication process may then continue in a conventional way.

公开(公告)号：US4967139A

公开(公告)日：1990-10-30

申请号：US509435

申请日：1990-04-16

Applicant: Giorgio Betti ,  Maurizio Zuffada ,  Fabrizio Sacchi ,  Silvano Gornati

Inventor： Giorgio Betti ,  Maurizio Zuffada ,  Fabrizio Sacchi ,  Silvano Gornati

IPC: G05F3/22

CPC classification number: G05F3/225 ,  Y10S323/907

Abstract: This variable-current source comprises a differential stage and a pair of voltage buffers which respectively receive, at the input, a variable input voltage and a reference voltage and are connected at the output to the differential stage. Both buffers comprise a resistor flown by a current which varies only as a function of the respective input voltage and of its resistance and therefore depends thermally exclusively on this resistance, and provide output voltages which depend upon these currents, so that the output current generated by the differential stage is temperature-independent.

公开(公告)号：US4949049A

公开(公告)日：1990-08-14

申请号：US342830

申请日：1989-04-25

Applicant: Edoardo Botti

Inventor： Edoardo Botti

IPC: H03F3/34 ,  H03F3/30 ,  H03F3/68

CPC classification number: H03F3/3081 ,  H03F3/68

Abstract: In an integrated amplifier comprising at least a pair of operational amplifiers which may be connected in a single-ended configuration to form a stereo amplifier or alternatively in a bridge configuration to increase the output dynamics, a single constant current generator for generating a current having a value which is twice the value of the bias current of the input stages of the two operational amplifiers, is connected between an inverting input of one of the two operational amplifiers and ground, and allows for elimination of the offset voltage without contributing to an increase, in any appreciable way, of the noise level at the inputs and without the signal applied to the input terminals of the integrated amplifier causing modulation problems.

公开(公告)号：US4947231A

公开(公告)日：1990-08-07

申请号：US259254

申请日：1988-10-18

Applicant: Sergio Palara ,  Mario Paparo ,  Roberto Pellicano'

Inventor： Sergio Palara ,  Mario Paparo ,  Roberto Pellicano'

IPC: H01L21/331 ,  H01L21/761 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/861

CPC classification number: H01L21/761 ,  H01L27/0658

Abstract: The integrated structure consists of circuit components made by diffusion of dopes in a semiconductor substrate. Each of said components is situated inside a respective insulating pocket to which is applied a voltage falling between the minimum and the maximum voltage applied to the components contained in the corresponding pocket. p

公开(公告)号：US4918370A

公开(公告)日：1990-04-17

申请号：US356810

申请日：1989-05-25

Applicant: Edoardo Botti ,  Massimo Nisetto

Inventor： Edoardo Botti ,  Massimo Nisetto

IPC: H03F1/00 ,  H03K17/28

CPC classification number: H03K17/28

Abstract: This low voltage-controlled, stand-by electronic circuit with delayed switch off, comprises a switching circuit defining a stand-by input receiving a stand-by switching signal and an output, and a delay circuit generating a delayed switch off signal. The switching circuit comprises a controlled current source having two control inputs, one whereof is connected to the stand-by input for switching on the controlled current source upon receiving the stand-by switching signal and the other of the inputs is connected to the delay circuit. The delay circuit is also connected to the stand-by input and receives therefrom the stand-by switching signal for generating the delayed switch off signal, so that the controlled current source is switched on upon receiving the stand-by switching signal and remains on in absence of the stand-by switching signal and of the delayed switch off signal, the controlled current source being switched off by the delayed switch off signal on the second control input.

公开(公告)号：US4914316A

公开(公告)日：1990-04-03

申请号：US283232

申请日：1988-12-12

Applicant: Domenico Rossi ,  Giovanni Pietrobon ,  Sandro Storti ,  Carlo Cini

Inventor： Domenico Rossi ,  Giovanni Pietrobon ,  Sandro Storti ,  Carlo Cini

IPC: H02H7/08 ,  H03K17/00 ,  H03K17/06 ,  H03K17/24 ,  H03K17/695

CPC classification number: H03K17/24 ,  H03K17/063

Abstract: A circuit for holding a MOS power transistor in a conduction state on the occurrence of an outage in the voltage supply, being of a type which comprises a first MOS transistor having its source connected to a line of the voltage supply and its drain connected to the gate of the power transistor, further comprises a diode connected between the drain of the first transistor and the gate of the power transistor, and a second transistor of the MOS type having its gate connected to the gate of the first transistor drain connected to the gate of the power transistor. The circuit prevents the gate capacitance of the power transistor from becoming discharged on a failure of the voltage supply, thus holding that transistor in a conducting state.

公开(公告)号：US4875020A

公开(公告)日：1989-10-17

申请号：US287299

申请日：1988-12-21

Applicant: Vincenzo Daniele ,  Marco M. Monti ,  Michele Taliercio ,  Piero Capocelli

Inventor： Vincenzo Daniele ,  Marco M. Monti ,  Michele Taliercio ,  Piero Capocelli

IPC: H01L27/04 ,  G06J1/00 ,  H01L21/82 ,  H01L21/822 ,  H03G3/02 ,  H03G5/02

CPC classification number: G06J1/00

Abstract: An integrated analog circuit having a circuit topology and intrinsic characteristics which may be selected by digital control means is formed by batteries of similar circuit components arranged substantially in parallel or in a matrix array, anyone of which may be isolated or not by means of a dedicated integrated switch and by alternative interconnection paths among the different circuit components and/or batteries of circuit components, which may be also be selected by closing a relative integrated switch. A dedicated nonvolatile memory, integrated on the same chip may be permanently programmed and determine a certain configuration of all the integrated switches thus selected a particlar component or more components of each of said batteries of functionally similar components, and/or selecting a certain interconnection path among the different circuit components in order to form a functional integrated circuit having the desired topology and intrinsic characteristics. The integrated nonvolatile memory is programmed by means of a software program which may take as input data the desired values of the different parameters which determine the intrinsic characteristics of the functional analog circuit and the type of functional analog circuit itself.