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    Neural network classifier using array of two-gate non-volatile memory cells
    331.
    发明授权
    Neural network classifier using array of two-gate non-volatile memory cells 有权

    公开(公告)号：US10699779B2

    公开(公告)日：2020-06-30

    申请号：US16382013

    申请日：2019-04-11

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

    IPC: G11C16/04 ,  G11C11/54 ,  G06N3/04 ,  H01L29/423 ,  G11C16/14 ,  H01L27/11521 ,  G11C16/10

    Abstract: A neural network device having a first plurality of synapses that includes a plurality of memory cells. Each memory cell includes a floating gate over a first portion of a channel region and a first gate over a second portion of the channel region. The memory cells are arranged in rows and columns. A plurality of first lines each electrically connect together the first gates in one of the memory cell rows, a plurality of second lines each electrically connect together the source regions in one of the memory cell rows, and a plurality of third lines each electrically connect together the drain regions in one of the memory cell columns. The first plurality of synapses receives a first plurality of inputs as electrical voltages on the plurality of third lines, and provides a first plurality of outputs as electrical currents on the plurality of second lines.

    Split-gate flash memory array with byte erase operation
    334.
    发明授权
    Split-gate flash memory array with byte erase operation 有权

    公开(公告)号：US10607703B2

    公开(公告)日：2020-03-31

    申请号：US16042000

    申请日：2018-07-23

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hsuan Liang ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Nhan Do ,  Hieu Van Tran

    IPC: G11C16/16 ,  G11C16/04 ,  H01L27/11521

    Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

    System and method for storing multibit data in non-volatile memory
    337.
    发明授权
    System and method for storing multibit data in non-volatile memory 有权

    公开(公告)号：US10515694B2

    公开(公告)日：2019-12-24

    申请号：US16148304

    申请日：2018-10-01

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Nhan Do ,  Hieu Van Tran

    IPC: G11C11/56 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

    Abstract: A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current. Alternately, a first voltage is generated from the first read current, a second voltage is generated from the second read current, whereby the offset value is applied to the second voltage, wherein the first and second voltages are combined to form a third voltage, and then the program state is determined using the third voltage.

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