公开(公告)号：US20140103521A1

公开(公告)日：2014-04-17

申请号：US13652937

申请日：2012-10-16

Applicant: STMICROELECTRONICS PTE. LTD

Inventor： Yonggang Jin ,  How Yuan HWANG

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An electronic device may include a bottom interconnect layer and an integrated circuit (IC) carried by the bottom interconnect layer. The electronic device may further include an encapsulation material on the bottom interconnect layer and laterally surrounding the IC. The electronic device may further include electrically conductive pillars on the bottom interconnect layer extending through the encapsulation material. At least one electrically conductive pillar and adjacent portions of encapsulation material may have a reduced height with respect to adjacent portions of the IC and the encapsulation material and may define at least one contact recess. The at least one contact recess may be spaced inwardly from a periphery of the encapsulation material.

Abstract translation: 电子设备可以包括底部互连层和由底部互连层承载的集成电路（IC）。 电子设备还可以包括底部互连层上的封装材料并横向包围IC。 电子器件还可以包括穿过封装材料的底部互连层上的导电柱。 至少一个导电柱和封装材料的相邻部分可以相对于IC和封装材料的相邻部分具有减小的高度，并且可以限定至少一个接触凹部。 所述至少一个接触凹部可以与所述封装材料的周边向内间隔开。

公开(公告)号：US20140091443A1

公开(公告)日：2014-04-03

申请号：US14032075

申请日：2013-09-19

Applicant: STMicroelectronics Pte Ltd ,  STMicroelectronics (Malta) Ltd

Inventor： Roseanne Duca ,  Kim-Yong Goh ,  Xueren Zhang ,  Kevin Formosa

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49541 ,  G01P1/023 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/1815 ,  H05K3/303 ,  H05K3/3421 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2224/45099

Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.

Abstract translation: 半导体器件的表面贴装封装具有：封装，容纳至少一个包含半导体材料的管芯; 以及电接触引线，从封装凸出以电耦合到电路板的接触焊盘; 封装具有设计成面向电路板的顶表面的主面，该主面具有设计成用于机械耦合到电路板的耦合特征，以增加安装封装的谐振频率。 耦合特征设想至少一个第一耦合凹槽，其限定在从主面开始的封装内，被设计成由固定到电路板的对应耦合元件接合，从而限制安装的封装的移动。

公开(公告)号：US08644053B2

公开(公告)日：2014-02-04

申请号：US13953626

申请日：2013-07-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Olivier Le Neel

IPC: G11C11/00

CPC classification number: G11C13/0002 ,  G11C11/21 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/33 ,  G11C2213/71

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Abstract translation: 形成集成电路，其具有位于半导体衬底上方的电介质堆叠中的存储器单元的阵列。 每个存储单元具有两个可调电阻器和两个加热元件。 电介质材料将加热元件与可调电阻分开。 一个加热元件通过加热来改变其中一个电阻器的电阻以将数据写入存储单元。 另一个加热元件通过加热来改变另一个电阻器的电阻，从而擦除来自存储单元的数据。

公开(公告)号：US20130314972A1

公开(公告)日：2013-11-28

申请号：US13953626

申请日：2013-07-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Olivier Le Neel

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G11C11/21 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/33 ,  G11C2213/71

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Abstract translation: 形成集成电路，其具有位于半导体衬底上方的电介质堆叠中的存储器单元的阵列。 每个存储单元具有两个可调电阻器和两个加热元件。 电介质材料将加热元件与可调电阻分开。 一个加热元件通过加热来改变其中一个电阻器的电阻以将数据写入存储单元。 另一个加热元件通过加热来改变另一个电阻器的电阻，从而擦除来自存储单元的数据。