公开(公告)号：US20250132893A1

公开(公告)日：2025-04-24

申请号：US18910731

申请日：2024-10-09

Applicant: STMicroelectronics International N.V.

Inventor： Pierre-Alexandre BLANC ,  Benjamin SARTORI

IPC: H04L9/06 ,  G06F7/58

Abstract: The present description concerns a method of verification, implemented by an electronic device, of a matrix used for the implementation of a data cipher algorithm comprising, for the generation of the matrix, the use of a first function and of a second function, the verification method comprising a verification using a final portion of the output data of the first function.

公开(公告)号：US20250132675A1

公开(公告)日：2025-04-24

申请号：US18906913

申请日：2024-10-04

Applicant: STMicroelectronics International N.V.

Inventor： Marco Giovanni FONTANA ,  Romino CRETONE

IPC: H02M3/158 ,  H02M1/088 ,  H03K17/687

Abstract: Provided is voltage regulator circuit including an input node for receiving an input supply voltage, an output node for producing an output regulated voltage, and a switchable pass element arranged between the input and output nodes. A comparator circuit compares the output regulated voltage to a dynamic threshold to produce a control signal to control the switchable pass element. The control signal being asserted results in the switchable pass element being turned on, and vice-versa. A threshold selection and shaping circuit shapes the output regulated voltage or the dynamic threshold so that: (i) in response to assertion of the control signal, the difference between the dynamic threshold and the output regulated voltage is abruptly increased and subsequently gradually decreased towards a target static value, and (ii) in response to de-assertion of the control signal, the difference is abruptly increased and subsequently gradually decreased towards a target static value.

公开(公告)号：US20250130550A1

公开(公告)日：2025-04-24

申请号：US18825669

申请日：2024-09-05

Applicant: STMicroelectronics International N.V.

Inventor： Donato Carpentieri ,  Daniele Mangano ,  Gianluca De Piano ,  Luigi Zaffarana

IPC: G05B19/4099

Abstract: A system-on-chip (SoC) including a memory is manufactured with a security feature configured to be enabled either in response to a set of SoC pads being asserted to respective security enablement values, or in response to a security key location in the memory having stored therein a key different from a security disablement key. During electrical wafer sorting (EWS), the security feature is disabled in response to a configuration of respective disablement values being applied to the set of SoC pads while, with the security feature disabled, the security key location in the memory is configured to have written therein a candidate disablement key. After EWS, the SoC pads are forced to respective non-transitory security enablement values wherein the security feature is enabled, and subsequent disablement of the security feature remains facilitated in response to the candidate disablement key being found to match the security disablement key.

公开(公告)号：US20250130129A1

公开(公告)日：2025-04-24

申请号：US18915158

申请日：2024-10-14

Applicant: STMicroelectronics International N.V.

Inventor： Filippo DANIELE ,  Enri DUQI ,  Lorenzo BALDO

IPC: G01L19/04 ,  G01L9/00 ,  G01L13/02

Abstract: A pressure sensor has a body having a first chamber and a second chamber hermetically separated from the first chamber; a first detection structure which is arranged in the first chamber, has a first deformable element and a first buried cavity within the first detection structure, wherein the first deformable element is configured to undergo a deformation as a function of a pressure difference between the first chamber and the first buried cavity. The sensor also has a second detection structure which is arranged in the second chamber, has a second deformable element and a second buried cavity within the second detection structure, wherein the second deformable element is configured to undergo a deformation as a function of a pressure difference between the second chamber and the second buried cavity. The sensor also has a first channel that extends into the body and is configured to fluidically couple the first buried cavity with the second chamber; and a second channel that extends into the body and is configured to fluidically couple the second buried cavity to the first chamber.

公开(公告)号：US20250123758A1

公开(公告)日：2025-04-17

申请号：US18988348

申请日：2024-12-19

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA

IPC: G06F3/06 ,  G11C7/10 ,  G11C11/418 ,  G11C11/419

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.

公开(公告)号：US20250116764A1

公开(公告)日：2025-04-10

申请号：US18783160

申请日：2024-07-24

Applicant: STMicroelectronics International N.V.

Inventor： Pascal Mellot

IPC: G01S7/4912 ,  G01S7/4914 ,  G01S7/4915 ,  G01S17/89

Abstract: An example heterodyne sensor of the present disclosure includes one or more optical mixers and an array of pixels. The optical mixers are configured to combine a reference light beam with one or more return light beams in order to generate one or more beat signals. Each pixel of the array of pixels includes a single-photon avalanche diode configured to receive a corresponding one of the one or more beat signals and to generate an output signal as a function of a light intensity of a received beat signal, and a digital counter configured to generate a count value based on the output signal of the single-photon avalanche diode.

公开(公告)号：US20250112605A1

公开(公告)日：2025-04-03

申请号：US18884508

申请日：2024-09-13

Applicant: STMicroelectronics International N.V.

Inventor： Luv PANDEY

IPC: H03F3/45

Abstract: In accordance with various embodiments of the present disclosure, an amplifier is provided. In some embodiments, the amplifier comprises a first amplifier stage, a second amplifier stage, a common mode sense amplifier stage, a first common mode feedback (CMFB) loop involving the first amplifier stage, the second amplifier stage, and the common mode sense amplifier stage, and a second CMFB loop involving only the first amplifier stage.

公开(公告)号：US20250112110A1

公开(公告)日：2025-04-03

申请号：US18375716

申请日：2023-10-02

Applicant: STMicroelectronics International N.V.

Inventor： Florian PERMINJAT ,  Fabrice DE MORO

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/40

Abstract: An integrated circuit package includes a support substrate with front connection pads on a front surface thereof and rear connection pads on a rear surface thereof. An integrated circuit device is mounted to the support substrate in flip chip orientation with a front face of the integrated circuit device facing the front surface of the support substrate. A thermally conductive heat spreader is mounted adjacent a rear face of the integrated circuit device. External direct thermal paths thermally couple a top surface of the thermally conductive heat spreader to the rear surface of the support substrate. Each external direct thermal path includes a first portion on and in direct contact with thermally conductive heat spreader, a second portion on and in direct contact with an external side surface of the support substrate and a third portion on and in direct contact with the rear surface of the support substrate.

公开(公告)号：US20250110161A1

公开(公告)日：2025-04-03

申请号：US18818009

申请日：2024-08-28

Applicant: STMicroelectronics International N.V.

Inventor： Gaetano Cosentino

IPC: G01R29/08 ,  G01R17/02 ,  G01R19/02

Abstract: A radiofrequency detector comprises a squarer circuit comprising first and second branches coupled between a voltage supply and ground, the first branch comprising at least a first squarer transistor receiving a RF sinusoidal input voltage, the first squarer transistor being coupled to the voltage supply through a respective load, the second branch comprising a second reference transistor being coupled to the voltage supply through a respective load, an output voltage being formed at an output node of the first branch and a reference voltage being formed at a respective output node coupled to the load of the second branch, a squared voltage being obtained by a difference voltage of the output voltage and reference voltage, wherein the circuit is configured to feed back to a control electrode of the second reference transistor a feedback signal that is a function of the difference voltage.

公开(公告)号：US12266927B2

公开(公告)日：2025-04-01

申请号：US18207493

申请日：2023-06-08

Applicant: STMicroelectronics International N.V.

Inventor： Radhakrishnan Sithanandam

IPC: H02H9/04 ,  H01L23/528 ,  H01L27/02 ,  H01L27/06 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/87 ,  H01L29/73 ,  H01L49/02

Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.