Method for measuring ambient light and corresponding integrated device

    公开(公告)号:US11808624B2

    公开(公告)日:2023-11-07

    申请号:US17500432

    申请日:2021-10-13

    CPC classification number: G01J1/4204 G01J1/44 G01J2001/446

    Abstract: In an embodiment a method for measuring ambient light includes successively synchronizing optical signal acquisition phases with extinction phases of a disruptive light source, wherein the disruptive light source periodically provides illumination phases and the extinction phases, accumulating, in each acquisition phase, photo-generated charges by at least one photosensitive pixel comprising a pinned photodiode, transferring the accumulated photo-generated charges to an integration node and integrating, for each pixel, the transferred charges on the integration node during a series of the successive acquisition phases.

    DEVICE AND METHOD FOR VOLTAGE DROP COMPENSATION

    公开(公告)号:US20230344357A1

    公开(公告)日:2023-10-26

    申请号:US18342159

    申请日:2023-06-27

    CPC classification number: H02M3/33553 H02M1/08

    Abstract: The present disclosure relates to a voltage source device comprising: a voltage converter for generating a supply voltage at an output node of the voltage converter based on a feedback signal provided on a feedback line; at least one switch coupled between the output node of the voltage converter and an output terminal of the voltage source device; and at least one further switch configured to selectively couple the feedback line to: the output node of the voltage converter during a first regulation mode; and to the output terminal of the voltage source device during a second regulation mode.

    DEVICE FOR COPYING A CURRENT
    36.
    发明公开

    公开(公告)号:US20230327621A1

    公开(公告)日:2023-10-12

    申请号:US18189665

    申请日:2023-03-24

    Inventor: Vratislav Michal

    CPC classification number: H03F3/45179 H03F1/0205

    Abstract: In an embodiment a device includes an input node configured to receive a first current, an output node configured to provide a second current determined by the first current, a first resistor having a first terminal connected to the input node and a second terminal coupled to a first node configured to receive a first supply voltage, a first MOS transistor having a source connected to the first node and a drain coupled to the output node of the device, a second resistor having a first terminal connected to a gate of the first MOS transistor, a biasing circuit configured to provide a biasing voltage on a second terminal of the second resistor and a first capacitor connected between the input node and the gate of the first MOS transistor.

    Connection of several circuits of an electronic chip

    公开(公告)号:US11764151B2

    公开(公告)日:2023-09-19

    申请号:US17580055

    申请日:2022-01-20

    CPC classification number: H01L23/528 H01L23/50 H01L23/5226

    Abstract: An electronic chip includes a shared strip with first and second spaced apart portions extending along a direction of elongation and an intermediate connecting portion extending between the first and second portions. The second portion is connected to a pad that has a greater surface area than the second portion. The first portion is formed by a first plurality of metallic strips. Metallic strips of the first plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips. The second portion is formed by a second plurality of metallic strips. Metallic strips of the second plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips.

    Optoelectronic device
    38.
    发明授权

    公开(公告)号:US11740416B2

    公开(公告)日:2023-08-29

    申请号:US17546314

    申请日:2021-12-09

    CPC classification number: G02B6/4239 G02B6/4213 G02B6/4274

    Abstract: An optoelectronic element is located in a package. The package includes a first optical block and a second optical block that are attached to each other by a bonding layer. One of the first and second optical blocks is attached to lateral walls of the package by glue. The material of the bonding layer is configured to induce less stress to the first and second optical blocks than the glue.

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