公开(公告)号：US07460047B2

公开(公告)日：2008-12-02

申请号：US11832144

申请日：2007-08-01

Applicant: Yuxing Zhang ,  Xiaoru Gao

Inventor： Yuxing Zhang ,  Xiaoru Gao

IPC: H03M1/66

CPC classification number: G09G3/3614 ,  G09G2320/0247 ,  H03M1/68

Abstract: A calibrator circuit and method for VCOM voltage adjustment for an LCD includes using integrated programmable resistive arrays. The method uses two DACs and three integrated circuit arrays to provide all of the advantages of VCOM calibrator circuits using external resistive voltage-dividers. The integrated circuit resistor arrays reduce the number of external components and PCB space. The method used is suitable for higher resolution adjustment of the VCOM voltage and no calculation is required in the whole adjustment procedure, which saves labor cost, time and enables automation of the calibrator fabrication.

Abstract translation: 用于LCD的VCOM电压调整的校准器电路和方法包括使用集成可编程电阻阵列。 该方法使用两个DAC和三个集成电路阵列，以提供使用外部电阻分压器的VCOM校准器电路的所有优点。 集成电路电阻阵列减少了外部元件数量和PCB空间。 所使用的方法适用于VCOM电压的更高分辨率调整，并且在整个调整过程中不需要计算，从而节省人工成本，节省时间并实现校准器制造的自动化。

公开(公告)号：US09000831B2

公开(公告)日：2015-04-07

申请号：US14073924

申请日：2013-11-07

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Fei Wang ,  KunKun Zheng

IPC: H03K17/687 ,  H03K17/10

CPC classification number: H03K17/102 ,  H03K2217/0054

Abstract: A pass gate circuit includes a first transistor coupled between an input node (receiving an input signal) and an output node (outputting an output signal). A second transistor is configured to generate a voltage difference in response to a bias current flowing therethrough, wherein that voltage difference is applied between a first gate of the first transistor and the output node. A differential amplifier functions to compare the voltage at the output node to a reference voltage and generate the bias current in response to that comparison.

Abstract translation: 通路电路包括耦合在输入节点（接收输入信号）和输出节点（输出输出信号）之间的第一晶体管。 第二晶体管被配置为响应于流过其中的偏置电流产生电压差，其中该电压差被施加在第一晶体管的第一栅极和输出节点之间。 差分放大器用于将输出节点处的电压与参考电压进行比较，并根据该比较产生偏置电流。

公开(公告)号：US08854106B2

公开(公告)日：2014-10-07

申请号：US13925032

申请日：2013-06-24

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Fei Wang ,  Snow Qi ,  Jackson Ding

IPC: H03K5/00 ,  H03K19/0185

CPC classification number: H03K19/018514

Abstract: A level shifting circuit includes a current mirror that generates a first bias current and a second bias current (proportional to the first bias current with a first ratio). A first level shifter is coupled between a first input node (receiving a first input signal) and a first output node coupled to an input of the current mirror. The first level shifter applies a first voltage variation to the first input signal in response to the first bias current. A second level is coupled between a second input node (receiving a second input signal) and a second output node coupled to an output of the current mirror. The second level shifter applies a second voltage variation (associated with the first voltage variation) to the second input signal in response to the second bias current.

Abstract translation: 电平移位电路包括产生第一偏置电流的电流镜和与第一偏置电流成比例的第二偏置电流。 第一电平移位器耦合在第一输入节点（接收第一输入信号）和耦合到当前反射镜的输入端的第一输出节点之间。 第一电平移位器响应于第一偏置电流向第一输入信号施加第一电压变化。 第二级耦合在第二输入节点（接收第二输入信号）和耦合到当前反射镜的输出端的第二输出节点之间。 第二电平移位器响应于第二偏置电流而将第二电压变化（与第一电压变化相关联）施加到第二输入信号。

公开(公告)号：US08829950B2

公开(公告)日：2014-09-09

申请号：US13713285

申请日：2012-12-13

Applicant: STMicroelectronics R&D Co. Ltd. (Shanghai)

Inventor： Tina Shen ,  Anderson Yin

IPC: H03K3/00 ,  H04L25/08 ,  H03K4/02 ,  H03K3/78

CPC classification number: H03K3/78 ,  H03K4/023 ,  H04L25/08

Abstract: A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus.

Abstract translation: 本地互连网络（LIN）驱动器电路采用施加到耦合到LIN总线的驱动器晶体管的栅极的充电/放电电流。 充电电流包括恒定的充电电流和额外的软充电电流，而放电电流包括恒定的放电电流和额外的软放电电流。 作为软充电/放电元件的结果，LIN总线上的电磁辐射显着减少。

公开(公告)号：US20140184305A1

公开(公告)日：2014-07-03

申请号：US14073924

申请日：2013-11-07

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Fei WANG ,  KunKun ZHENG

IPC: H03K17/10

CPC classification number: H03K17/102 ,  H03K2217/0054

Abstract: A pass gate circuit includes a first transistor coupled between an input node (receiving an input signal) and an output node (outputting an output signal). A second transistor is configured to generate a voltage difference in response to a bias current flowing therethrough, wherein that voltage difference is applied between a first gate of the first transistor and the output node. A differential amplifier functions to compare the voltage at the output node to a reference voltage and generate the bias current in response to that comparison.

Abstract translation: 通路电路包括耦合在输入节点（接收输入信号）和输出节点（输出输出信号）之间的第一晶体管。 第二晶体管被配置为响应于流过其中的偏置电流产生电压差，其中该电压差被施加在第一晶体管的第一栅极和输出节点之间。 差分放大器用于将输出节点处的电压与参考电压进行比较，并根据该比较产生偏置电流。

公开(公告)号：US08724279B2

公开(公告)日：2014-05-13

申请号：US12892726

申请日：2010-09-28

Applicant: Zhaoang Yang ,  Haiyang Liu ,  Zhongxuan Tu ,  Jianxin Zhang

Inventor： Zhaoang Yang ,  Haiyang Liu ,  Zhongxuan Tu ,  Jianxin Zhang

IPC: H02H3/08 ,  H02H9/02

CPC classification number: G06K7/0013

Abstract: In one embodiment, a system for providing short circuit protection is disclosed. The system has a supply circuit and a series switch. The supply circuit has a supply input and a supply output, and is configured to deliver an output current at the supply output, and to disable the supply output if the output current exceeds a first current limit. The series switch coupled between the supply output of the supply circuit and a supply node, and the supply node is configured to be coupled to a load.

Abstract translation: 在一个实施例中，公开了一种用于提供短路保护的系统。 该系统具有电源电路和串联开关。 供电电路具有电源输入和电源输出，并且被配置为在电源输出端传送输出电流，并且如果输出电流超过第一电流限制，则禁止电源输出。 耦合在电源电路的电源输出和供电节点之间的串联开关和供电节点被配置为耦合到负载。

公开(公告)号：US20140015699A1

公开(公告)日：2014-01-16

申请号：US14028244

申请日：2013-09-16

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Jian Hua Zhao ,  Yuxing Zhang

IPC: H03M1/06

CPC classification number: H03M1/06 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/468

Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

Abstract translation: 在一个实施例中，公开了一种将模拟输入值转换为数字输出值的方法。 执行逐次逼近。 模拟输入被量化为第一量化值，其使用DAC被转换为第一模拟值。 从模拟输入值中减去第一个模拟值，形成第一个残差。 量化第一残余物以形成第二量化值，并且通过使用DAC将第二量化值转换为第二模拟值并从第一残留值减去第二模拟值来形成第二残差。 然后将第二残基量化以形成第三量子化值。 第一，第二和第三量化值被转换为数字输出值。 第一，第二和第三量化值各自至少有三个等级。

公开(公告)号：US08537046B2

公开(公告)日：2013-09-17

申请号：US13331611

申请日：2011-12-20

Applicant: Jian Hua Zhao ,  Yuxing Zhang

Inventor： Jian Hua Zhao ,  Yuxing Zhang

IPC: H03M1/12

CPC classification number: H03M1/06 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/468

Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

公开(公告)号：US20130222053A1

公开(公告)日：2013-08-29

申请号：US13854395

申请日：2013-04-01

Applicant: STMicroelectronics R&D (Shanghai) Co., Ltd.

Inventor： Jian Hua ZHAO ,  Wadeo Ou

IPC: H03G3/00

CPC classification number: H03G3/004 ,  H03G3/002 ,  H03G3/3089

Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.

Abstract translation: 实现功率高效的高频缓冲器的电路和方法。 检测缓冲信号的幅度并与输入信号的幅度进行比较。 比较结果可以反馈到数字控制缓冲器，以保持输出增益不变。 通过使用反馈控制，即使负载条件或信号频率变化，也可以将缓冲器保持在最合适的偏置状态。

公开(公告)号：US08248287B2

公开(公告)日：2012-08-21

申请号：US12965663

申请日：2010-12-10

Applicant: Jianhua Zhao ,  Reed Yang

Inventor： Jianhua Zhao ,  Reed Yang

IPC: H03M1/66

CPC classification number: H03M1/80 ,  H03M1/66

Abstract: For voltage interpolation amplifiers used in digital-to-analog converter architecture, the number of input differential pairs required by the voltage interpolation amplifier may be reduced such that an N-bit voltage interpolation amplifier comprises N+1 input differential pairs connected through a resistor attenuation network to provide a binary-weighted effective transconductance. In comparison to conventional voltage interpolation amplifier designs, the number of input differential pairs and power consumed by the circuit is significantly reduced, thereby creating a more area- and power-efficient voltage interpolation amplifier.

Abstract translation: 对于用于数模转换器架构的电压内插放大器，可以减小电压内插放大器所需的输入差分对的数量，使得N位电压内插放大器包括通过电阻衰减连接的N + 1个输入差分对 网络提供二进制加权有效跨导。 与传统的电压内插放大器设计相比，输入差分对的数量和电路消耗的功率大大降低，从而创建了一个面积更大且功耗更高的电压内插放大器。