公开(公告)号：US08319257B2

公开(公告)日：2012-11-27

申请号：US12325697

申请日：2008-12-01

申请人： Kohtaro Hayashi ,  Akinori Shibayama

发明人： Kohtaro Hayashi ,  Akinori Shibayama

IPC分类号： H01L27/118

CPC分类号： G06F17/5072 ,  H01L27/0207

摘要： A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions in parallel with and a fixed distance apart from the gate electrodes arranged at both ends in a gate length direction on active regions of the transistors and, when the transistors have plural gate electrodes with different gate widths, extending the projected parts to the outside of the active regions by a necessary length, a gate connecting step of, when gate patterns and contact regions are connected to the gate electrodes of the transistors, connecting the gate electrodes and the dummy gates according to a positional relation between the gate electrodes and the dummy gates, and a wiring step of wiring a metal layer. It is possible to design a semiconductor device having a smaller area than that in the past and with a less design man-hour.

摘要翻译： 一种用于半导体器件的布局设计方法包括：布置晶体管的步骤，形成伪栅极的伪栅极形成步骤，其具有与包括栅电极或栅电极的形状相同的形状以及从栅电极的有源区域的突出部分 在与晶体管的有源区域的栅极长度方向上配置的栅极电极平行且固定距离的位置上，并且当晶体管具有多个具有不同栅极宽度的栅电极时，将投影部分延伸到 在有源区域外部具有必要的长度;栅极连接步骤，当栅极图案和接触区域连接到晶体管的栅电极时，根据栅电极和栅电极之间的位置关系连接栅电极和伪栅极; 虚拟栅极和布线金属层的布线步骤。 可以设计具有比过去小的面积和较少设计工时的半导体器件。

公开(公告)号：US06985396B2

公开(公告)日：2006-01-10

申请号：US10619578

申请日：2003-07-16

申请人： Akinori Shibayama

发明人： Akinori Shibayama

IPC分类号： G11C7/00

CPC分类号： G11C7/1006 ,  G11C2207/104

摘要： A semiconductor integrated circuit with integrated memory and data-processing logic portions is provided, with which productivity and yield can be improved. The semiconductor integrated circuit is provided with a memory, a plurality of logic portions that are capable of being connected to the memory, and a separation portion that connects one of the plurality of logic portions to the memory, while separating the other logic portions from the memory. One required logic portion of the plurality of logic portions is connected to the memory, and the other non-required logic portions are separated from the memory, by the separation portion. The semiconductor integrated circuit can be switched for a system LSI after wafer processing, so this enables a plurality of system LSIs to be manufactured using the same exposure masks, thus improving productivity. Furthermore, defective logic portions can be recovered, thus improving the yield.

摘要翻译： 提供具有集成存储器和数据处理逻辑部分的半导体集成电路，可以提高生产率和产量。 半导体集成电路设置有存储器，能够连接到存储器的多个逻辑部分和将多个逻辑部分之一连接到存储器的分离部分，同时将其它逻辑部分与 记忆。 多个逻辑部分中的一个所需的逻辑部分连接到存储器，并且另外的不需要的逻辑部分通过分离部分与存储器分离。 在晶片处理之后，半导体集成电路可以切换为系统LSI，因此能够使用相同的曝光掩模来制造多个系统LSI，从而提高生产率。 此外，可以恢复有缺陷的逻辑部分，从而提高产量。

公开(公告)号：US20050274983A1

公开(公告)日：2005-12-15

申请号：US11149350

申请日：2005-06-10

申请人： Kohtaro Hayashi ,  Akinori Shibayama

发明人： Kohtaro Hayashi ,  Akinori Shibayama

IPC分类号： G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L27/10

CPC分类号： G06F17/5072 ,  H01L27/0207

摘要： A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions in parallel with and a fixed distance apart from the gate electrodes arranged at both ends in a gate length direction on active regions of the transistors and, when the transistors have plural gate electrodes with different gate widths, extending the projected parts to the outside of the active regions by a necessary length, a gate connecting step of, when gate patterns and contact regions are connected to the gate electrodes of the transistors, connecting the gate electrodes and the dummy gates according to a positional relation between the gate electrodes and the dummy gates, and a wiring step of wiring a metal layer. It is possible to design a semiconductor device having a smaller area than that in the past and with a less design man-hour.

摘要翻译： 一种用于半导体器件的布局设计方法包括：布置晶体管的步骤，形成伪栅极的伪栅极形成步骤，其具有与包括栅电极或栅电极的形状相同的形状以及从栅电极的有源区域的突出部分 在与晶体管的有源区域的栅极长度方向上配置的栅极电极平行且固定距离的位置上，并且当晶体管具有多个具有不同栅极宽度的栅电极时，将投影部分延伸到 在有源区域外部具有必要的长度;栅极连接步骤，当栅极图案和接触区域连接到晶体管的栅电极时，根据栅电极和栅电极之间的位置关系连接栅电极和伪栅极; 虚拟栅极和布线金属层的布线步骤。 可以设计具有比过去小的面积和较少设计工时的半导体器件。

公开(公告)号：US06275434B1

公开(公告)日：2001-08-14

申请号：US09523205

申请日：2000-03-10

申请人： Toshio Yamada ,  Akinori Shibayama

发明人： Toshio Yamada ,  Akinori Shibayama

IPC分类号： G11C702

CPC分类号： G11C29/785 ,  G11C7/062 ,  G11C7/14 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4099 ,  H01L27/10808

摘要： A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time. As a result of such arrangement, even when there occurs a small current leakage from memory cells, it is possible to secure a long data retention time thereby making it possible to obtain a long refresh cycle period.

公开(公告)号：US5680071A

公开(公告)日：1997-10-21

申请号：US592676

申请日：1996-01-26

申请人： Manabu Senoh ,  Yoshitaka Mano ,  Akinori Shibayama

发明人： Manabu Senoh ,  Yoshitaka Mano ,  Akinori Shibayama

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/409 ,  H03K19/003 ,  H03K19/017 ,  H03K17/16

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K19/00315 ,  H03K19/01742

摘要： In a dynamic random access memory (DRAM), first and second output transistors form an NMOS-type tristate output buffer. Interposed between a gate electrode of the first output transistor and a data input/output terminal (DQ terminal) is an auxiliary transistor of which gate electrode is grounded and of which threshold voltage is lower than that of the first output transistor. Further interposed between the DQ terminal and a gate electrode of the second output transistor is another auxiliary transistor of which gate electrode is grounded and of which threshold voltage is lower than that of the second output transistor. Both auxiliary transistors lower gate voltages of both output transistors down to a negative voltage level such that both output transistors are maintained as cut off when a negative voltage is externally applied to the DQ terminal at the time of high impedance.

摘要翻译： 在动态随机存取存储器（DRAM）中，第一和第二输出晶体管形成NMOS型三态输出缓冲器。 第一输出晶体管的栅极电极和数据输入/输出端子（DQ端子）之间的辅助晶体管是栅电极接地的阈值电压低于第一输出晶体管的辅助晶体管。 进一步插在DQ端子和第二输出晶体管的栅电极之间的另一辅助晶体管是栅电极接地的阈值电压低于第二输出晶体管的辅助晶体管。 两个辅助晶体管将两个输出晶体管的栅极电压降低到负电压电平，使得当在高阻抗时将负电压外部施加到DQ端子时，两个输出晶体管保持为截止。

公开(公告)号：US5424629A

公开(公告)日：1995-06-13

申请号：US865363

申请日：1992-04-08

申请人： Atsushi Fujiwara ,  Akinori Shibayama

发明人： Atsushi Fujiwara ,  Akinori Shibayama

IPC分类号： G05F3/24 ,  G05F5/08

CPC分类号： G05F3/247

摘要： A power circuit for a semiconductor apparatus comprising an internal power voltage generating circuit generating an internal power voltage, an external power voltage detecting circuit, a power voltage switching circuit switching the internal power voltage to the external power voltage in response to the output of the external power voltage detecting circuit, and a switching signal setting circuit. The output of the power voltage switching circuit is the internal power voltage when power is first applied to the semiconductor device. The switching signal setting circuit provides the correct power voltage switching signals quickly to the power voltage switching circuit when power is applied and the external power voltage is not inputted to the apparatus at the early stage of power application.

摘要翻译： 一种用于半导体装置的电源电路，包括产生内部电源电压的内部电源电压产生电路，外部电源电压检测电路，电源电压切换电路，响应于外部的输出将内部电源电压切换到外部电源电压 电源电压检测电路和开关信号设定电路。 电源电压切换电路的输出是当第一次向半导体器件供电时的内部电源电压。 开关信号设定电路在供电时向电源电压切换电路提供正确的电源电压切换信号，并且在电源应用的早期阶段未将外部电源电压输入到设备。

公开(公告)号：US4316178A

公开(公告)日：1982-02-16

申请号：US113674

申请日：1980-01-21

申请人： Akinori Shibayama ,  Kenji Maio ,  Masao Hotta ,  Norio Yokozawa

发明人： Akinori Shibayama ,  Kenji Maio ,  Masao Hotta ,  Norio Yokozawa

IPC分类号： H03M1/10 ,  H03M1/00 ,  H03K13/02

CPC分类号： H03M1/1071 ,  H03M1/74

摘要： In a digital-to-analog converter having means to convert a digital input signal into an analog signal, processing means to evaluate an error attendant upon the conversion, and memory means to store the evaluated error; a digital-to-analog converter with a compensating circuit wherein the processing means comprises a ramp voltage generator, a clock pulse generator, and counting means to count clock pulses of the generator and to deliver the error on the basis of the count value of the clock pulses at each time when the ramp voltage exceeds the output of the conversion means.

摘要翻译： 在具有将数字输入信号转换为模拟信号的装置的数模转换器中，用于评估转换时伴随的误差的处理装置以及存储评估误差的存储装置; 具有补偿电路的数模转换器，其中所述处理装置包括斜坡电压发生器，时钟脉冲发生器和计数装置，用于对所述发生器的时钟脉冲进行计数，并基于所述发生器的计数值来递送所述误差 当斜坡电压超过转换装置的输出时，每个时钟脉冲。