公开(公告)号：US20100244195A1

公开(公告)日：2010-09-30

申请号：US12412702

申请日：2009-03-27

Applicant: Limin Lin ,  Bin Xie ,  Shu Yuan

Inventor： Limin Lin ,  Bin Xie ,  Shu Yuan

IPC: H01L29/20 ,  H01L21/302

CPC classification number: H01L33/0079

Abstract: A host substrate and method of making a host substrate for nitride based thin-film semiconductor devices are provided. According to one embodiment, the method includes the steps of providing a silicon layer; etching a pattern of holes in the silicon layer; plating the silicon layer with copper to fill the holes etched in the silicon layer; bonding the silicon layer to a gallium nitride (GaN) layer, the GaN layer attached to a sapphire substrate; and removing the sapphire substrate. The host substrate is configured to address the coefficient of thermal expansion (CTE) mismatch problem and reduce the amount of stress resulting from such CTE mismatch. A combination of metal and semiconductor materials provide for the desired thermal and electrical conductivity while providing for subsequent dicing and incorporation of the finished semiconductor devices into other circuits.

Abstract translation: 提供了一种主衬底和制造用于氮化物基薄膜半导体器件的主衬底的方法。 根据一个实施例，该方法包括提供硅层的步骤; 蚀刻硅层中的孔的图案; 用铜电镀硅层以填充蚀刻在硅层中的孔; 将所述硅层与氮化镓（GaN）层接合，所述GaN层附着在蓝宝石衬底上; 并去除蓝宝石衬底。 主机基板被配置为解决热膨胀系数（CTE）失配问题，并减少由这种CTE失配引起的应力的量。 金属和半导体材料的组合提供期望的热导电性和导电性，同时提供随后的切割和将成品半导体器件并入其它电路中。

公开(公告)号：US20100123241A1

公开(公告)日：2010-05-20

申请号：US12273434

申请日：2008-11-18

Applicant: Xunqing Shi ,  Bin Xie ,  Chang Hwa Chung

Inventor： Xunqing Shi ,  Bin Xie ,  Chang Hwa Chung

IPC: H01L23/04 ,  H01L21/00

CPC classification number: H01L23/16 ,  H01L21/76898 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06579 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Subject matter disclosed herein may relate to packaging for multi-chip semiconductor devices as may be used, for example, in flash memory devices. In an example embodiment, a semiconductor chip may comprise a through-silicon via and a sidewall pad.

Abstract translation: 本文公开的主题可涉及可用于例如闪存设备中的多芯片半导体器件的封装。 在示例性实施例中，半导体芯片可以包括穿硅通孔和侧壁衬垫。