公开(公告)号：US08324960B2

公开(公告)日：2012-12-04

申请号：US12849503

申请日：2010-08-03

Applicant: Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Yuwen Swei

Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Yuwen Swei

IPC: G05F1/10 ,  G05F3/02

CPC classification number: H02M3/07

Abstract: An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.

Abstract translation: 集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。 第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。 集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。

公开(公告)号：US08223576B2

公开(公告)日：2012-07-17

申请号：US12716430

申请日：2010-03-03

Applicant: Tien-Chun Yang ,  Chih-Chang Lin ,  Ming-Chieh Huang

Inventor： Tien-Chun Yang ,  Chih-Chang Lin ,  Ming-Chieh Huang

IPC: G11C5/14

CPC classification number: G11C5/145 ,  G11C11/4074

Abstract: A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage Vref.

Abstract translation: 提供了一种用于调节电荷泵的调节器。 调节器包括具有能够接收第一电压的第一输入端和能够接收用于确定启动或禁用电荷泵的第二电压的第二输入端的比较器。 第一电压与电荷泵的输出电压相关联。 第二电压与内部电源电压和参考电压Vref相关联。

公开(公告)号：US08217729B2

公开(公告)日：2012-07-10

申请号：US12706825

申请日：2010-02-17

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

IPC: H03B5/08

CPC classification number: H03L5/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03L7/099

Abstract: An integrated circuit includes an inductor-capacitor (LC) tank circuit coupled with a feedback loop. The LC tank circuit is configured to output an output signal having a peak voltage that is substantially equal to a direct current (DC) voltage level plus an amplitude. The feedback loop is capable of determining if the peak voltage of the output signal falls within a range between a first voltage level and a second voltage level for adjusting the amplitude of the output signal.

Abstract translation: 集成电路包括与反馈回路耦合的电感器 - 电容（LC）电路。 LC槽电路被配置为输出具有基本上等于直流（DC）电压电平加上幅度的峰值电压的输出信号。 反馈回路能够确定输出信号的峰值电压是否落在用于调节输出信号的幅度的第一电压电平和第二电压电平之间的范围内。

公开(公告)号：US20120019302A1

公开(公告)日：2012-01-26

申请号：US12843479

申请日：2010-07-26

Applicant: Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Ming-Chieh HUANG ,  Chih-Chang LIN

Inventor： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Ming-Chieh HUANG ,  Chih-Chang LIN

IPC: H03L5/00

CPC classification number: H03K19/018521

Abstract: A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.

Abstract translation: 电平移位器包括一个PMOS和两个NMOS晶体管。 第一NMOS晶体管的源极耦合到低电源电压。 输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。 输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。 输出信号耦合在PMOS和第一NMOS晶体管之间。 第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1， 输入信号为逻辑0。

公开(公告)号：US20110199063A1

公开(公告)日：2011-08-18

申请号：US12706825

申请日：2010-02-17

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

IPC: G05F1/10

CPC classification number: H03L5/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03L7/099

Abstract: An integrated circuit includes an inductor-capacitor (LC) tank circuit coupled with a feedback loop. The LC tank circuit is configured to output an output signal having a peak voltage that is substantially equal to a direct current (DC) voltage level plus an amplitude. The feedback loop is capable of determining if the peak voltage of the output signal falls within a range between a first voltage level and a second voltage level for adjusting the amplitude of the output signal.

Abstract translation: 集成电路包括与反馈回路耦合的电感器 - 电容（LC）电路。 LC槽电路被配置为输出具有基本上等于直流（DC）电压电平加上幅度的峰值电压的输出信号。 反馈回路能够确定输出信号的峰值电压是否落在用于调节输出信号的幅度的第一电压电平和第二电压电平之间的范围内。

公开(公告)号：US20100215139A1

公开(公告)日：2010-08-26

申请号：US12699458

申请日：2010-02-03

Applicant: Chih-Chang LIN ,  Tien-Chun Yang ,  Steven Swei

Inventor： Chih-Chang LIN ,  Tien-Chun Yang ,  Steven Swei

IPC: H03K23/00

CPC classification number: H03K21/38

Abstract: Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C1) and a second counter (e.g., counter C2), which, together with the first counter C1, perform the counting function for counter C. For example, if counter C is to count to the value N, then counter C1 counts, e.g., to N1, and counter C2 counts to N2 where N=N1+N2. For counter C1 to count to N1, N1 is loaded to counter C1. Similarly, for counter C2 to count to N2, N2 is loaded to counter C2. While counter C1 counts (e.g., to N1), N2 can be loaded to counter C2. After counter C1 finishes counting to N1, N2, if loaded, is available for counter C2 to start counting to this N2. Counters C1 and C2 can alternately count and thus provide continuous counting for counter C. Other embodiments and exemplary applications are also disclosed.

Abstract translation: 本文描述的实施例涉及计数器。 在一些实施例中，计数器可以用作分频器，例如在分数PLL中。 在一些实施例中，计数器（例如，主计数器或计数器C）包括第一计数器（例如，计数器C1）和第二计数器（例如，计数器C2），其与第一计数器C1一起执行计数功能 对于计数器C.例如，如果计数器C计数到值N，则计数器C1计数，例如，到N1，并且计数器C2计数到N2，其中N = N1 + N2。 对于计数器C1计数到N1，N1被加载到计数器C1。 类似地，对于计数器C2计数到N2，N2被加载到计数器C2。 当计数器C1计数（例如，到N1）时，可以将N2加载到计数器C2。 在计数器C1结束计数到N1之后，N2（如果加载）可用于计数器C2开始计数到这个N2。 计数器C1和C2可以交替地计数并因此为计数器C提供连续计数。还公开了其他实施例和示例性应用。

公开(公告)号：US07373618B1

公开(公告)日：2008-05-13

申请号：US11271269

申请日：2005-11-10

Applicant: Kei-Yong Khoo ,  Tao Feng ,  Debjyoti Paul ,  Chih-Chang Lin

Inventor： Kei-Yong Khoo ,  Tao Feng ,  Debjyoti Paul ,  Chih-Chang Lin

IPC: G06F17/50

CPC classification number: G06F17/504

Abstract: A system, method, computer program, and article of manufacture for generating a golden circuit including datapath components for equivalence checking of synthesized revised circuit. The method includes generating a set of static, dynamic and derived candidates for the datapath component subcircuit, evaluating the similarity degree for each candidate in relation to the revised circuits and selecting one candidate for implementation in the golden circuit. As a result, the subcircuit of datapath component in the golden circuit is replaced with the subcircuit which is more similar to the revised circuit to improve the efficiency of the equivalence checking.

Abstract translation: 一种用于产生包含用于合成修正电路的等效检查的数据通路组件的黄金电路的系统，方法，计算机程序和制造。 该方法包括为数据通路组件子电路生成一组静态，动态和导出候选，评估每个候选人相对于​​修订电路的相似度，并选择一个在黄金电路中实现的候选项。 结果，黄金电路中的数据路径分量的子电路被更换类似于修正电路的子电路所取代，以提高等效性检查的效率。

公开(公告)号：US07279822B2

公开(公告)日：2007-10-09

申请号：US11100556

申请日：2005-04-07

Applicant: Chin-Wen Chou ,  Eddie Cheng ,  Kuang-Ming Wu ,  Chih-Chang Lin

Inventor： Chin-Wen Chou ,  Eddie Cheng ,  Kuang-Ming Wu ,  Chih-Chang Lin

IPC: H01L41/09

CPC classification number: H01L41/044 ,  H02M3/158 ,  H05B41/2828 ,  Y02B70/1425

Abstract: A transformer level driving circuit mainly aims to drive a medium voltage system. It includes a control unit to generate a resonant frequency and output phase signal waveforms, and a medium voltage driving circuit which includes a floating level unit and a driving unit which receives a medium voltage electric input. The driving unit actuates opening and closing at different time to enable the floating level unit to output a voltage floating level thereby to drive a ceramic transformer to control the medium voltage system through a low voltage level.

Abstract translation: 变压器电平驱动电路主要用于驱动中压系统。 它包括一个产生谐振频率和输出相位信号波形的控制单元，以及包括一个浮置电平单元和一个接收中压电输入的驱动单元的中压驱动电路。 驱动单元在不同时间启动打开和关闭，以使浮动水平单元能够输出电压浮动电平，从而驱动陶瓷变压器以通过低电压电平控制中压系统。

公开(公告)号：US06848084B1

公开(公告)日：2005-01-25

申请号：US10327608

申请日：2002-12-20

Applicant: Manish Pandey ,  Mitchell W. Hines ,  Chih-Chang Lin

Inventor： Manish Pandey ,  Mitchell W. Hines ,  Chih-Chang Lin

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: This invention relates to method and apparatus for verification of circuit designs containing memories. At a register transfer abstraction level, verification of a circuit design requires showing that the register transfer language (RTL) abstraction of the design is logically equivalent to the design implementation represented at the logic (e.g., gate and/or flip-flop) and/or the transistor (e.g. implementation verification) abstraction levels, as well as logic simulation of the design RTL embedded in a system-level test bench for verification at the system-abstraction level.

Abstract translation: 本发明涉及用于验证包含存储器的电路设计的方法和装置。 在注册传输抽象级别，电路设计的验证要求显示设计的寄存器传输语言（RTL）抽象在逻辑上等同于在逻辑（例如，门和/或触发器）处表示的设计实现和/ 或晶体管（例如实现验证）抽象级别，以及嵌入在系统级测试台中的设计RTL的逻辑仿真，以便在系统抽象级别进行验证。

公开(公告)号：US09722818B2

公开(公告)日：2017-08-01

申请号：US14492237

申请日：2014-09-22

Applicant: Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03 ,  H04L25/06 ,  H04L25/08

CPC classification number: H04L25/03057 ,  H04L25/06 ,  H04L25/08

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.