公开(公告)号：US07486546B2

公开(公告)日：2009-02-03

申请号：US11806636

申请日：2007-06-01

Applicant: Min-Chuan Wang ,  Chih-Sheng Lin ,  Chia-Pao Chang ,  Keng-Li Su

Inventor： Min-Chuan Wang ,  Chih-Sheng Lin ,  Chia-Pao Chang ,  Keng-Li Su

IPC: G11C11/00

CPC classification number: G11C7/062 ,  G11C7/06 ,  G11C11/1673 ,  G11C11/5607 ,  G11C2207/063 ,  G11C2211/5634 ,  G11C2211/5645

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.

Abstract translation: 本发明提供一种多状态读出放大器，耦合到具有可变电阻的至少一个存储单元和多个参考单元。 耦合到存储器单元的输出端的第一电流镜电路根据通过存储单元的第一存储单元电流在第一节点产生第二存储单元电流。 耦合到参考单元的输出端的第二电流镜电路根据通过参考单元的多个第一参考电流在多个第二节点处产生多个第二参考电流。 耦合到第一节点，第二节点和地的负载电路为第二存储器单元电流和第二参考电流提供相等的负载，以分别在第一节点处产生存储单元电压和多个参考电压 第二个节点。

公开(公告)号：US20080007992A1

公开(公告)日：2008-01-10

申请号：US11806636

申请日：2007-06-01

Applicant: Min-Chuan Wang ,  Chih-Sheng Lin ,  Chia-Pao Chang ,  Keng-Li Su

Inventor： Min-Chuan Wang ,  Chih-Sheng Lin ,  Chia-Pao Chang ,  Keng-Li Su

IPC: G11C11/02 ,  G11C7/06

CPC classification number: G11C7/062 ,  G11C7/06 ,  G11C11/1673 ,  G11C11/5607 ,  G11C2207/063 ,  G11C2211/5634 ,  G11C2211/5645

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.

Abstract translation: 本发明提供一种多状态读出放大器，耦合到具有可变电阻的至少一个存储单元和多个参考单元。 耦合到存储器单元的输出端的第一电流镜电路根据通过存储单元的第一存储单元电流在第一节点产生第二存储单元电流。 耦合到参考单元的输出端的第二电流镜电路根据通过参考单元的多个第一参考电流在多个第二节点处产生多个第二参考电流。 耦合到第一节点，第二节点和接地的负载电路为第二存储器单元电流和第二参考电流提供相等的负载，以分别在第一节点处产生存储器单元电压和多个参考电压 第二个节点。

公开(公告)号：US09086455B2

公开(公告)日：2015-07-21

申请号：US13326331

申请日：2011-12-15

Applicant: Hsin-Chi Lai ,  Chih-Sheng Lin ,  Pi-Feng Chiu ,  Zhe-Hui Lin

Inventor： Hsin-Chi Lai ,  Chih-Sheng Lin ,  Pi-Feng Chiu ,  Zhe-Hui Lin

IPC: G01R31/02 ,  G01R31/3185 ,  G01R31/28 ,  G01R31/317 ,  H01L21/66

CPC classification number: G01R31/318513 ,  G01R31/2812 ,  G01R31/31717 ,  H01L22/22

Abstract: A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector.

Abstract translation: 提供了设置在第一和第二芯片之间的通过硅通孔（TSV）的测试和修复设备。 第一和第二开关的第一端子耦合到TSV的第一端子。 第三和第四开关的第一端子耦合到TSV的第二端子。 第一电阻器的第一端子耦合到第一电压。 第一选择器耦合在第二开关的第二端子和第一电阻器之间。 第二选择器耦合在第四开关的第二端和第二电压之间。 第一控制电路检测第二开关的第二端子，并控制第一开关，第二开关和第一选择器。 第二控制电路控制第三开关，第四开关和第二选择器。

公开(公告)号：US20120139092A1

公开(公告)日：2012-06-07

申请号：US12968285

申请日：2010-12-15

Applicant: Keng-Li Su ,  Hsin-Chi Lai ,  Chih-Sheng Lin ,  Zhe-Hui Lin

Inventor： Keng-Li Su ,  Hsin-Chi Lai ,  Chih-Sheng Lin ,  Zhe-Hui Lin

IPC: H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/642 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541

Abstract: A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.

Abstract translation: 提供了包括第一芯片，第二芯片，屏蔽层和多个导电凸块的多芯片堆叠结构。 第二芯片堆叠在第一芯片上。 第二芯片具有多个贯穿硅通孔（TSV）结构以导通参考电压。 屏蔽层和多个导电凸块设置在第一芯片和第二芯片之间，并且电连接到多个TSV结构。 屏蔽层可以隔离噪声并改善两个相邻芯片之间的信号耦合。

公开(公告)号：US20120018723A1

公开(公告)日：2012-01-26

申请号：US12967932

申请日：2010-12-14

Applicant: Keng-Li SU ,  Chih-Sheng Lin ,  Wen-Pin Lin ,  John H. Lau

Inventor： Keng-Li SU ,  Chih-Sheng Lin ,  Wen-Pin Lin ,  John H. Lau

IPC: H01L23/58 ,  H01L21/66

CPC classification number: H01L22/34

Abstract: A test structure including at least one ground pad, an input pad, at least one first through-silicon via (TSV), at least one second TSV and an output pad is disclosed. The ground pad receives a ground signal during a test mode. The input pad receives a test signal during the test mode. The first TSV is coupled to the input pad. The output pad is coupled to the second TSV. No connection line occurs between the first and the second TSVs. During the test mode, a test result is obtained according to the signal of at least one of the first and the second TSVs, and structural characteristics can be obtained according to the test result.

Abstract translation: 公开了包括至少一个接地焊盘，输入焊盘，至少一个第一穿透硅通孔（TSV），至少一个第二TSV和输出焊盘的测试结构。 接地焊盘在测试模式下接收接地信号。 在测试模式期间，输入焊盘接收测试信号。 第一TSV耦合到输入板。 输出焊盘耦合到第二TSV。 在第一和第二TSV之间不发生连接线。 在测试模式期间，根据第一和第二TSV中的至少一个的信号获得测试结果，并且可以根据测试结果获得结构特征。

公开(公告)号：US20100320478A1

公开(公告)日：2010-12-23

申请号：US12710454

申请日：2010-02-23

Applicant: Chih-Sheng Lin ,  Che-Hsiung Wu

Inventor： Chih-Sheng Lin ,  Che-Hsiung Wu

IPC: H01L33/00 ,  H01L21/30

CPC classification number: H01L33/145 ,  H01L33/38

Abstract: A light-emitting diode device includes: a substrate; a light-emitting layered structure disposed on the substrate and including a first cladding layer, an active layer, and a second cladding layer; a first electrode; a second electrode disposed on the light-emitting layered structure; and a current blocking region provided in the light-emitting layered structure below the second electrode, and having a main portion that is aligned below and is as large as the second electrode, and an extension portion extending from the main portion and protruding beyond the second electrode to a distance ranging from 3 μm to 20 μm.

Abstract translation: 发光二极管装置包括：基板; 发光层状结构，其设置在所述基板上，并且包括第一包层，有源层和第二包层; 第一电极; 设置在所述发光层状结构上的第二电极; 以及电流阻挡区，设置在所述第二电极下方的所述发光层状结构中，并且具有与所述第二电极相对的下方且与所述第二电极一致的主要部分，以及从所述主体部延伸并突出超过所述第二电极的延伸部 电极到3μm至20μm的距离。

公开(公告)号：US20100311605A1

公开(公告)日：2010-12-09

申请号：US12567192

申请日：2009-09-25

Applicant: Chih-Sheng Lin ,  Yao-Chen Chuang ,  Sz-Hao Chen

Inventor： Chih-Sheng Lin ,  Yao-Chen Chuang ,  Sz-Hao Chen

IPC: C40B30/04 ,  C40B40/18 ,  C40B40/04 ,  C40B40/10 ,  C40B40/06 ,  C40B50/08

CPC classification number: G01N33/542 ,  B82Y30/00 ,  G01N33/54353 ,  G01N33/587

Abstract: A sensing platform includes: a plurality of metal nanoparticles; a plurality of aggregate inducers each comprising first and second functional groups different from each other, and the first functional group of the aggregate inducers being in contact with the metal nanoparticles; and a plurality of recognition molecules for binding the metal nanoparticles and for interacting with a target to recognize the target, wherein the second functional group of the aggregate inducers is free from being in contact with the metal nanoparticles, and is used to induce the metal nanoparticles to aggregate after the recognition molecules interact with the target.

Abstract translation: 感测平台包括：多个金属纳米颗粒; 多个集合诱导剂，其各自包含彼此不同的第一和第二官能团，并且所述聚集诱导剂的第一官能团与所述金属纳米颗粒接触; 以及用于结合金属纳米粒子并与靶相互作用以识别靶的多个识别分子，其中聚集诱导剂的第二官能团不与金属纳米颗粒接触，并用于诱导金属纳米粒子 在识别分子与靶物相互作用后聚集。

公开(公告)号：US20090141574A1

公开(公告)日：2009-06-04

申请号：US12155787

申请日：2008-06-10

Applicant: Min Chuan Wang ,  Chih Sheng Lin ,  Keng Li Su ,  Wei Chun Chang

Inventor： Min Chuan Wang ,  Chih Sheng Lin ,  Keng Li Su ,  Wei Chun Chang

IPC: G11C7/02

CPC classification number: G11C11/5607 ,  G11C11/16 ,  G11C29/08 ,  G11C2211/5634

Abstract: The present invention relates to a memory accessing circuit, which is for accessing a memory circuit with 2N impedance states. The memory accessing circuit comprises a testing signal generating circuit, for generating a testing signal by detecting the impedance state of the memory circuit; a reference signal generating circuit, for generating 2N−1 reference signals by detecting the impedance states of a reference circuit having 2N−1 impedance paths; a median signal generating circuit, for generating (2N−1)−1, median signals by receiving the 2N−1 reference signals; and a comparing circuit, for comparing the testing signal and the (2N−1) median signals. The present invention further provides a memory accessing method thereof.

Abstract translation: 本发明涉及一种用于访问具有2N个阻抗状态的存储器电路的存储器存取电路。 存储器访问电路包括测试信号发生电路，用于通过检测存储器电路的阻抗状态来产生测试信号; 参考信号发生电路，用于通过检测具有2N-1个阻抗路径的参考电路的阻抗状态来产生2N-1个参考信号; 中间信号发生电路，用于通过接收2N-1个参考信号来产生（2N-1）-1个中间信号; 以及用于比较测试信号和（2N-1）个中值信号的比较电路。 本发明还提供一种其存储器访问方法。