公开(公告)号：US07973692B2

公开(公告)日：2011-07-05

申请号：US12669482

申请日：2008-06-06

申请人： Erik Chmelar ,  Choshu Ito ,  William Loh

发明人： Erik Chmelar ,  Choshu Ito ,  William Loh

IPC分类号： H03M1/36

CPC分类号： H03M1/1215 ,  H03M1/002 ,  H03M1/361

摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.

摘要翻译： 本发明的各种实施例提供了用于模数转换的系统和方法。 例如，公开了一种基于锁存器的模数转换器，其包括与一组比较器的第一交错，选择器电路和锁存器。 该组比较器可操作以将模拟输入与相应的参考电压进行比较，并且与时钟相位同步。 选择器电路可操作以至少部分地基于选择器输入来选择该组比较器之一的输出。 从所选择的输出中导出第一交错输出。 锁存器接收来自第二交错的第二交织输出，并且在时钟相位被断言时是透明的。 选择器输入包括锁存器的输出。

公开(公告)号：US07944655B2

公开(公告)日：2011-05-17

申请号：US12128108

申请日：2008-05-28

申请人： Tze Wee Chen ,  William Loh ,  Choshu Ito

发明人： Tze Wee Chen ,  William Loh ,  Choshu Ito

IPC分类号： H02H9/00

CPC分类号： H01H59/0009 ,  H02H9/046

摘要： An ESD protection circuit for protecting a host circuit coupled to a signal pad from an ESD event occurring at the signal pad includes at least one MEMS switch which is electrically connected to the signal pad. The MEMS switch includes a first contact structure adapted for connection to the signal pad, and a second contact structure adapted for connection to a voltage supply source. The first and second contact structures are coupled together during the ESD event for shunting an ESD current from the signal pad to the voltage supply source. The first and second contact structures are electrically isolated from one another in the absence of the ESD event. At least one of the first and second contact structures includes a passivation layer for reducing contact adhesion between the first and second contact structures.

摘要翻译： 用于保护耦合到信号垫的主机电路与在信号焊盘处发生的ESD事件的ESD保护电路包括至少一个电连接到信号焊盘的MEMS开关。 MEMS开关包括适于连接到信号焊盘的第一接触结构和适于连接到电压源的第二接触结构。 在ESD事件期间，第一和第二接触结构耦合在一起，用于将ESD电流从信号焊盘分流到电压源。 在没有ESD事件的情况下，第一和第二接触结构彼此电隔离。 第一和第二接触结构中的至少一个包括用于减小第一和第二接触结构之间的接触粘附的钝化层。

公开(公告)号：US07777996B2

公开(公告)日：2010-08-17

申请号：US11174135

申请日：2005-06-30

申请人： William M. Loh ,  Ken Doniger ,  Payman Zarkesh-Ha ,  Jau-Wen Chen ,  Choshu Ito

发明人： William M. Loh ,  Ken Doniger ,  Payman Zarkesh-Ha ,  Jau-Wen Chen ,  Choshu Ito

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.

摘要翻译： 一种用于保护电路的系统和方法。 该系统包括保护电路，该保护电路包括逆变器和耦合到逆变器的电容器。 逆变器和电容器使用电路核心的逻辑电路实现，并且逆变器分流通过电容器的静电放电ESD电流。 根据本文公开的系统和方法，由于保护电路并联电路使用电路核心的逻辑电路来分流ESD电流，所以在不需要大的FET的情况下实现ESD保护。 此外，保护电路保护电路免受常规FET无法保护的ESD事件。

公开(公告)号：US20090303093A1

公开(公告)日：2009-12-10

申请号：US12134523

申请日：2008-06-06

申请人： Sergey Gribok ,  Choshu Ito ,  William Loh ,  Erik Chmelar

发明人： Sergey Gribok ,  Choshu Ito ,  William Loh ,  Erik Chmelar

IPC分类号： H03M1/00

CPC分类号： H03M1/182 ,  H03M1/002 ,  H03M1/004 ,  H03M1/361 ,  H03M1/367

摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods.

摘要翻译： 本发明的各种实施例提供了用于模数转换的系统和方法。 例如，公开了一种流水线模数转换器，其包括两个或更多个比较器。 比较器中的第一个可操作以在断言第一时钟时将模拟输入与第一参考电压进行比较，并且第二比较器可用于在断言第二时钟时将模拟输入与第二参考电压进行比较。 流水线模数转换器还包括具有至少第一层多路复用器和第二层多路复用器的复用器树。 第一层多路复用器接收第一比较器的输出和第二比较器的输出，并且第二层多路复用器接收从第一层多路复用器导出的输出。 第二层复用器提供输出位。 位使能集合用作对第一层多路复用器和第二层多路复用器的选择器输入，并且位使能集包括来自先前位周期的一个或多个输出位。

公开(公告)号：US07493576B2

公开(公告)日：2009-02-17

申请号：US11349356

申请日：2006-02-07

申请人： William Loh ,  Li Lynn Ooi ,  Choshu Ito

发明人： William Loh ,  Li Lynn Ooi ,  Choshu Ito

IPC分类号： G06F17/50 ,  G06F9/00

CPC分类号： G06F17/5036

摘要： Methods and structure for improved design remediation for previously inexplicable damage to core circuits of an application circuit design caused by CDM ESD events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Features and aspects hereof automatically alter an application circuit design to provide remediation by various techniques to reduce the magnitude of such inductive coupling and to thereby reduce susceptibility of the application circuit to damage from CDM ESD events. The modifications may be enforced as rules during initial design of the application circuit or as reconfiguration of a design in response to simulation to discover inappropriate coupling in the design.

摘要翻译： 改进设计修复的方法和结构，以前由于CDM ESD事件引起的应用电路设计的核心电路的莫名其妙的损害。 本发明的特征和方面注意到，对应用电路设计的核心电路的这种以前的莫名其妙的损害是由非核心电路和应用电路设计的核心电路之间的电感耦合引起的。 其特征和方面自动改变应用电路设计，以通过各种技术提供补救以减少这种电感耦合的幅度，从而降低应用电路对CDM ESD事件的损害的敏感性。 在应用电路的初始设计期间，修改可以被执行为规则，或者作为响应于模拟的设计的重新配置以发现设计中的不适当的耦合。

公开(公告)号：US07458044B2

公开(公告)日：2008-11-25

申请号：US11349358

申请日：2006-02-07

申请人： Choshu Ito ,  Li Lynn Ooi ,  William Loh

发明人： Choshu Ito ,  Li Lynn Ooi ,  William Loh

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5036

摘要： Methods and structure for improved simulation of CDM ESD events and for remediation of circuit designs correcting for previously inexplicable damage to core circuits of an application circuit design caused by such events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Improved simulation techniques in accordance with features and aspects hereof may predict where such inductive coupling may cause damage to core circuits. Other features and aspects hereof may alter an application circuit design to provide remediation by automated insertion of additional buffer circuitry to core traces of the core circuitry that may be impacted by such inductive coupling.

摘要翻译： 改进CDM ESD事件仿真和修复电路设计的方法和结构，以纠正由此类事件引起的应用电路设计对核心电路的以前不可思议的损害。 本发明的特征和方面注意到，对应用电路设计的核心电路的这种以前的莫名其妙的损害是由非核心电路和应用电路设计的核心电路之间的电感耦合引起的。 根据其特征和方面的改进的仿真技术可以预测这种感应耦合可能会对核心电路造成损害。 本发明的其它特征和方面可以改变应用电路设计，以通过将附加的缓冲电路自动插入到可能受这种电感耦合影响的核心电路的芯线迹来提供补救。