公开(公告)号：US07656340B2

公开(公告)日：2010-02-02

申请号：US12134523

申请日：2008-06-06

申请人： Sergey Gribok ,  Choshu Ito ,  William Loh ,  Erik Chmelar

发明人： Sergey Gribok ,  Choshu Ito ,  William Loh ,  Erik Chmelar

IPC分类号： H03M1/38

CPC分类号： H03M1/182 ,  H03M1/002 ,  H03M1/004 ,  H03M1/361 ,  H03M1/367

摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods.

摘要翻译： 本发明的各种实施例提供了用于模数转换的系统和方法。 例如，公开了一种流水线模数转换器，其包括两个或更多个比较器。 比较器中的第一个可操作以在断言第一时钟时将模拟输入与第一参考电压进行比较，并且第二比较器可用于在断言第二时钟时将模拟输入与第二参考电压进行比较。 流水线模数转换器还包括具有至少第一层多路复用器和第二层多路复用器的复用器树。 第一层多路复用器接收第一比较器的输出和第二比较器的输出，并且第二层多路复用器接收从第一层多路复用器导出的输出。 第二层复用器提供输出位。 位使能集合用作对第一层多路复用器和第二层多路复用器的选择器输入，并且位使能集包括来自先前位周期的一个或多个输出位。

公开(公告)号：US20090303093A1

公开(公告)日：2009-12-10

申请号：US12134523

申请日：2008-06-06

申请人： Sergey Gribok ,  Choshu Ito ,  William Loh ,  Erik Chmelar

发明人： Sergey Gribok ,  Choshu Ito ,  William Loh ,  Erik Chmelar

IPC分类号： H03M1/00

CPC分类号： H03M1/182 ,  H03M1/002 ,  H03M1/004 ,  H03M1/361 ,  H03M1/367

摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods.

摘要翻译： 本发明的各种实施例提供了用于模数转换的系统和方法。 例如，公开了一种流水线模数转换器，其包括两个或更多个比较器。 比较器中的第一个可操作以在断言第一时钟时将模拟输入与第一参考电压进行比较，并且第二比较器可用于在断言第二时钟时将模拟输入与第二参考电压进行比较。 流水线模数转换器还包括具有至少第一层多路复用器和第二层多路复用器的复用器树。 第一层多路复用器接收第一比较器的输出和第二比较器的输出，并且第二层多路复用器接收从第一层多路复用器导出的输出。 第二层复用器提供输出位。 位使能集合用作对第一层多路复用器和第二层多路复用器的选择器输入，并且位使能集包括来自先前位周期的一个或多个输出位。

公开(公告)号：US20100194616A1

公开(公告)日：2010-08-05

申请号：US12669481

申请日：2008-06-06

申请人： Erik Chmelar ,  Choshu Ito ,  William Loh

发明人： Erik Chmelar ,  Choshu Ito ,  William Loh

IPC分类号： H03M1/12

CPC分类号： H03M1/1215 ,  H03M1/002 ,  H03M1/361

摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.

摘要翻译： 本发明的各种实施例提供了用于模数转换的系统和方法。 例如，公开了一种重新定时的模数转换器，其包括第一组子电平交织和第二组子电平交织。 第一组子电平交织包括与第一时钟相位同步的第一组比较器的第一子电平交织以及与第二时钟相位同步的第二组比较器的第二子电平交织。 第二组子电平交织包括与第三组比较器同步到第三时钟相位的第三子电平交织以及与第四时钟相位同步的第四组比较器的第四子电平交织。 至少部分地基于来自第二组子电平交织组的输出和第三组比较器中的一个，至少部分地基于第一组比较器的输出，选择第一组比较器中的一个， 子级交错。 在上述实施例的一些情况下，第一子电平交织的输出和第二子电平交织的输出被同步到第三时钟相位，并且第三子电平交织的输出和 第四子电平交错同步到第一时钟相位。

公开(公告)号：US20100195776A1

公开(公告)日：2010-08-05

申请号：US12669482

申请日：2008-06-06

申请人： Erik Chmelar ,  Choshu Ito ,  William Loh

发明人： Erik Chmelar ,  Choshu Ito ,  William Loh

IPC分类号： H04L7/02 ,  H03K5/153

CPC分类号： H03M1/1215 ,  H03M1/002 ,  H03M1/361

摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.

摘要翻译： 本发明的各种实施例提供了用于模数转换的系统和方法。 例如，公开了一种基于锁存器的模数转换器，其包括与一组比较器的第一交错，选择器电路和锁存器。 该组比较器可操作以将模拟输入与相应的参考电压进行比较，并且与时钟相位同步。 选择器电路可操作以至少部分地基于选择器输入来选择该组比较器之一的输出。 从所选择的输出中导出第一交错输出。 锁存器接收来自第二交错的第二交织输出，并且在时钟相位被断言时是透明的。 选择器输入包括锁存器的输出。

公开(公告)号：US07956790B2

公开(公告)日：2011-06-07

申请号：US12669481

申请日：2008-06-06

申请人： Erik Chmelar ,  Choshu Ito ,  William Loh

发明人： Erik Chmelar ,  Choshu Ito ,  William Loh

IPC分类号： H03M1/34

CPC分类号： H03M1/1215 ,  H03M1/002 ,  H03M1/361

摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.

摘要翻译： 本发明的各种实施例提供了用于模数转换的系统和方法。 例如，公开了一种重新定时的模数转换器，其包括第一组子电平交织和第二组子电平交织。 第一组子电平交织包括与第一时钟相位同步的第一组比较器的第一子电平交织以及与第二时钟相位同步的第二组比较器的第二子电平交织。 第二组子电平交织包括与第三组比较器同步到第三时钟相位的第三子电平交织以及与第四时钟相位同步的第四组比较器的第四子电平交织。 至少部分地基于来自第二组子电平交织组的输出和第三组比较器中的一个，至少部分地基于第一组比较器的输出，选择第一组比较器中的一个， 子级交错。 在上述实施例的一些情况下，第一子电平交织的输出和第二子电平交织的输出被同步到第三时钟相位，并且第三子电平交织的输出和 第四子电平交错同步到第一时钟相位。

公开(公告)号：US20090304066A1

公开(公告)日：2009-12-10

申请号：US12134501

申请日：2008-06-06

申请人： Erik Chmelar ,  Choshu Ito ,  William Loh

发明人： Erik Chmelar ,  Choshu Ito ,  William Loh

IPC分类号： H03H7/30 ,  H03K5/159

CPC分类号： H04L25/03057 ,  H03M1/002 ,  H03M1/004 ,  H03M1/361 ,  H03M1/367

摘要： Various embodiments of the present invention provide systems and methods for signal equalization, and in some cases analog to digital conversion. For example, an analog to digital converter is disclosed that includes a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level. A selector circuit selects the first adjustment feedback to generate the reference indicator when the decision output is the first logic level, and selects the second adjustment feedback to generate the reference indicator when the decision output is the second logic level.

摘要翻译： 本发明的各种实施例提供用于信号均衡的系统和方法，并且在某些情况下提供模数转换。 例如，公开了一种模数转换器，其包括：比较器组，其接收参考指示符，并且可操作以至少部分地基于模拟输入与对应于参考指示符的参考阈值的比较来提供判定输出。 包括具有第一调整计算电路和第二调整计算电路的量程选择滤波器。 所述第一调整计算电路至少部分地基于所述判定输出是第一逻辑电平的推测来计算第一调整反馈值，并且所述第二调整计算电路可操作以至少至少计算第二调整反馈值 部分原因是决策输出是第二个逻辑电平。 当决策输出是第一逻辑电平时，选择器电路选择第一调整反馈以产生参考指示符，并且当决策输出是第二逻辑电平时，选择第二调整反馈以产生参考指示符。

公开(公告)号：US08121186B2

公开(公告)日：2012-02-21

申请号：US12134501

申请日：2008-06-06

申请人： Erik Chmelar ,  Choshu Ito ,  William Loh

发明人： Erik Chmelar ,  Choshu Ito ,  William Loh

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L25/03057 ,  H03M1/002 ,  H03M1/004 ,  H03M1/361 ,  H03M1/367

摘要： Various embodiments of the present invention provide systems and methods for signal equalization, and in some cases analog to digital conversion. For example, an analog to digital converter is disclosed that includes a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level. A selector circuit selects the first adjustment feedback to generate the reference indicator when the decision output is the first logic level, and selects the second adjustment feedback to generate the reference indicator when the decision output is the second logic level.

摘要翻译： 本发明的各种实施例提供用于信号均衡的系统和方法，并且在某些情况下提供模数转换。 例如，公开了一种模数转换器，其包括：比较器组，其接收参考指示符，并且可操作以至少部分地基于模拟输入与对应于参考指示符的参考阈值的比较来提供判定输出。 包括具有第一调整计算电路和第二调整计算电路的量程选择滤波器。 所述第一调整计算电路至少部分地基于所述判定输出是第一逻辑电平的推测来计算第一调整反馈值，并且所述第二调整计算电路可操作以至少至少计算第二调整反馈值 部分原因是决策输出是第二个逻辑电平。 当决策输出是第一逻辑电平时，选择器电路选择第一调整反馈以产生参考指示符，并且当决策输出是第二逻辑电平时，选择第二调整反馈以产生参考指示符。

公开(公告)号：US07973692B2

公开(公告)日：2011-07-05

申请号：US12669482

申请日：2008-06-06

申请人： Erik Chmelar ,  Choshu Ito ,  William Loh

发明人： Erik Chmelar ,  Choshu Ito ,  William Loh

IPC分类号： H03M1/36

CPC分类号： H03M1/1215 ,  H03M1/002 ,  H03M1/361

摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.

摘要翻译： 本发明的各种实施例提供了用于模数转换的系统和方法。 例如，公开了一种基于锁存器的模数转换器，其包括与一组比较器的第一交错，选择器电路和锁存器。 该组比较器可操作以将模拟输入与相应的参考电压进行比较，并且与时钟相位同步。 选择器电路可操作以至少部分地基于选择器输入来选择该组比较器之一的输出。 从所选择的输出中导出第一交错输出。 锁存器接收来自第二交错的第二交织输出，并且在时钟相位被断言时是透明的。 选择器输入包括锁存器的输出。

公开(公告)号：US07696915B2

公开(公告)日：2010-04-13

申请号：US12108791

申请日：2008-04-24

申请人： Erik Chmelar ,  Choshu Ito

发明人： Erik Chmelar ,  Choshu Ito

IPC分类号： H03M1/36

CPC分类号： H03M1/182 ,  H03M1/002 ,  H03M1/004 ,  H03M1/361 ,  H03M1/367

摘要： An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.

摘要翻译： ADC电路包括多个比较器和耦合到比较器的控制器。 每个比较器可操作以产生指示表示施加到ADC电路的输入信号的第一信号与对应的参考信号之间的差的输出。 控制器可操作以执行以下至少之一：（i）在给定的采样周期期间激活比较器的子集; 和（ii）根据输入信号的电平来控制比较器的相应参考信号的电平。 给定采样周期内的多个有源比较器不小于输入信号被量化的区域数量的一个。

公开(公告)号：US20090267821A1

公开(公告)日：2009-10-29

申请号：US12108791

申请日：2008-04-24

申请人： Erik Chmelar ,  Choshu Ito

发明人： Erik Chmelar ,  Choshu Ito

IPC分类号： H03M1/36

CPC分类号： H03M1/182 ,  H03M1/002 ,  H03M1/004 ,  H03M1/361 ,  H03M1/367

摘要： An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.

摘要翻译： ADC电路包括多个比较器和耦合到比较器的控制器。 每个比较器可操作以产生指示表示施加到ADC电路的输入信号的第一信号与对应的参考信号之间的差的输出。 控制器可操作以执行以下至少之一：（i）在给定的采样周期期间激活比较器的子集; 和（ii）根据输入信号的电平来控制比较器的相应参考信号的电平。 给定采样周期内的多个有源比较器不小于输入信号被量化的区域数量的一个。