公开(公告)号：US08760593B2

公开(公告)日：2014-06-24

申请号：US12221615

申请日：2008-08-05

Applicant: Po-Lin Chen ,  Kuo-Yuan Tu ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Shu-Feng Wu

Inventor： Po-Lin Chen ,  Kuo-Yuan Tu ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Shu-Feng Wu

IPC: G02F1/136 ,  H01L29/04 ,  H01L21/00

CPC classification number: H01L29/458 ,  H01L27/124

Abstract: A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.

Abstract translation: 薄膜晶体管（TFT）包括栅电极，栅极电介质层，半导体层，源极/漏极，钝化层和保护层。 栅电极设置在基板上。 栅介质层覆盖栅电极和衬底。 半导体层设置在栅极电介质层上并在栅电极上方。 半导体层具有设置在沟道区两侧的栅电极和源极/漏极区上方的沟道区。 源极/漏极设置在半导体层的源极/漏极区域上，并且每个具有设置在半导体层的源极/漏极区域上的势垒层和设置在阻挡层上的导电层。 钝化层设置在源/漏电极的表面上。 保护层设置在衬底，钝化层和半导体层的沟道区之上。

公开(公告)号：US08704220B2

公开(公告)日：2014-04-22

申请号：US13444860

申请日：2012-04-12

Applicant: Hao-Lin Chiu ,  Chi-Jui Lin ,  Shu-Wei Tsao ,  Chun-Nan Lin ,  Po-Liang Yeh ,  Shine-Kai Tseng

Inventor： Hao-Lin Chiu ,  Chi-Jui Lin ,  Shu-Wei Tsao ,  Chun-Nan Lin ,  Po-Liang Yeh ,  Shine-Kai Tseng

IPC: H01L29/12

CPC classification number: H01L29/41733 ,  H01L29/42384 ,  H01L29/7869

Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.

Abstract translation: 提供了包括源极，漏极，氧化物半导体层，栅极和栅极绝缘体层的有源器件。 源极包括彼此平行的第一条纹电极和与其连接的第一连接电极。 漏极包括彼此平行的第二条状电极和与其连接的第二连接电极，其中第一条形电极和第二条状电极彼此平行，电隔离并交替布置，并且之间形成之字形沟槽。 门沿着之字形沟槽延伸。 氧化物半导体层与源极和漏极接触，其中氧化物半导体层和每个第一条带电极之间的接触面积基本上等于每个第一条带电极的布局面积，并且每个第二条带电极之间的接触面积基本上等于 每个第二条纹电极的布局区域。

公开(公告)号：US08686178B2

公开(公告)日：2014-04-01

申请号：US13420177

申请日：2012-03-14

Applicant: Chun-Nan Lin ,  Kai-Wei Lin ,  A-Mei Huang ,  Tzyh-Chyuan Hour ,  Shyh-Chyun Yang ,  Yeong-Shiau Pu ,  Jan-Gowth Chang

Inventor： Chun-Nan Lin ,  Kai-Wei Lin ,  A-Mei Huang ,  Tzyh-Chyuan Hour ,  Shyh-Chyun Yang ,  Yeong-Shiau Pu ,  Jan-Gowth Chang

IPC: C07C69/75 ,  C07C233/58 ,  A61K31/122

CPC classification number: A61K31/16 ,  A61K31/215 ,  C07C69/757 ,  C07C231/00 ,  C07C237/26 ,  C07C2603/48 ,  C07J63/008

Abstract: The present invention is correlated with a derivative of 18β-glycyrrhetinic acid apt to suppressing cancer cells, which is selected from a group comprising of structure I and structure II: wherein residue R1 is selected from one of CH3 and CH2C6H5, residue R2 is selected from one of COOCH3, COOCH2CH3, COOCH(CH3)2, CONHCH2CH3, CONHCH2CH2CH3, and CONHCH2(CH3)2, and residue R3 is selected from one of COOCH2CH3, COOCH(CH3)2, CONHCH2CH3, CONHCH2CH2CH3, and CONHCH2(CH3)2.

Abstract translation: 本发明与选自结构I和结构II的组中选择的能够抑制癌细胞的18β-甘草次酸的衍生物相关：其中残基R1选自CH 3和CH 2 C 6 H 5之一，残基R 2选自 COOCH 3，COOCH 2 CH 3，COOCH（CH 3）2，CONHCH 2 CH 3，CONHCH 2 CH 2 CH 3和CONHCH 2（CH 3）2之一，残基R 3选自COOCH 2 CH 3，COOCH（CH 3）2，CONHCH 2 CH 3，CONHCH 2 CH 2 CH 3和CONHCH 2（CH 3）2 。

公开(公告)号：US20130168682A1

公开(公告)日：2013-07-04

申请号：US13424382

申请日：2012-03-20

Applicant: Chen-Yuan Tu ,  Yih-Chyun Kao ,  Shu-Feng Wu ,  Chun-Nan Lin

Inventor： Chen-Yuan Tu ,  Yih-Chyun Kao ,  Shu-Feng Wu ,  Chun-Nan Lin

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/43 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/786 ,  H01L29/7869

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括栅极，沟道层，栅极绝缘层，源极，漏极和硅 - 氧化铝层。 栅极设置在基板上。 通道层设置在基板上。 沟道层与栅极重叠。 栅极绝缘层设置在栅极和沟道层之间。 源极和漏极设置在沟道层的两侧。 硅 - 氧化铝层设置在基板上并覆盖源极，漏极和沟道层。

公开(公告)号：US20130109752A1

公开(公告)日：2013-05-02

申请号：US13420177

申请日：2012-03-14

Applicant: Chun-Nan Lin ,  Kai-Wei Lin ,  A-Mei Huang ,  Tzyh-Chyuan Hour ,  Shyh-Chyun Yang ,  Yeong-Shiau Pu ,  Jan-Gowth Chang

Inventor： Chun-Nan Lin ,  Kai-Wei Lin ,  A-Mei Huang ,  Tzyh-Chyuan Hour ,  Shyh-Chyun Yang ,  Yeong-Shiau Pu ,  Jan-Gowth Chang

IPC: A61K31/215 ,  C07C237/26 ,  C07C231/00 ,  A61P35/00 ,  C07C67/02 ,  C07C69/757 ,  A61K31/16

CPC classification number: A61K31/16 ,  A61K31/215 ,  C07C69/757 ,  C07C231/00 ,  C07C237/26 ,  C07C2603/48 ,  C07J63/008

Abstract: The present invention is correlated with a derivative of 18β-glycyrrhetinic acid apt to suppressing cancer cells, which is selected from a group comprising of structure I and structure II: wherein residue R1 is selected from one of CH3 and CH2C6H5, residue R2 is selected from one of COOCH3, COOCH2CH3, COOCH(CH3)2, CONHCH2CH3, CONHCH2CH2CH3, and CONHCH2(CH3)2, and residue R3 is selected from one of COOCH2CH3, COOCH(CH3)2, CONHCH2CH3, CONHCH2CH2CH3, and CONHCH2(CH3)2.

Abstract translation: 本发明与适于抑制癌细胞的18beta-甘草次酸的衍生物相关，其选自结构I和结构II：其中残基R1选自CH 3和CH 2 C 6 H 5之一，残基R 2选自 COOCH3，COOCH2CH3，COOCH（CH3）2，CONHCH2CH3，CONHCH2CH2CH3和CONHCH2（CH3）2之一，残基R3选自COOCH2CH3，COOCH（CH3）2，CONHCH2CH3，CONHCH2CH2CH3和CONHCH2（CH3）2之一。

公开(公告)号：US08395149B2

公开(公告)日：2013-03-12

申请号：US12776484

申请日：2010-05-10

Applicant: Yih-Chyun Kao ,  Chun-Nan Lin ,  Li-Kai Chen ,  Wen-Ching Tsai

Inventor： Yih-Chyun Kao ,  Chun-Nan Lin ,  Li-Kai Chen ,  Wen-Ching Tsai

IPC: H01L29/786 ,  H01L29/12

CPC classification number: H01L29/7869

Abstract: A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode. The passivation layer has a groove formed therein, and the groove surrounds the oxide semiconductor layer.

Abstract translation: 提供了一种基板上的半导体器件结构及其制造方法。 半导体器件结构包括氧化物半导体晶体管和含有游离氢的钝化层。 半导体器件结构通过以下步骤形成。 在基板上形成栅电极。 栅介质层覆盖栅电极。 源极电极形成在栅极电介质层上。 在栅极电介质层上形成漏电极，与源电极分离，形成通道距离。 在栅极电介质层，源电极和漏电极以及源电极和漏电极之间形成氧化物半导体层。 氧化物半导体层进一步与源电极和漏电极电连接。 钝化层覆盖氧化物半导体层，源电极和漏电极。 钝化层在其中形成有凹槽，并且沟槽围绕氧化物半导体层。

公开(公告)号：US20120261755A1

公开(公告)日：2012-10-18

申请号：US13477077

申请日：2012-05-22

Applicant: Po-Lin Chen ,  Chun-Nan Lin ,  Shu-Feng Wu ,  Wen-Ching Tsai

Inventor： Po-Lin Chen ,  Chun-Nan Lin ,  Shu-Feng Wu ,  Wen-Ching Tsai

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/458 ,  H01L27/124 ,  H01L27/1255

Abstract: A pixel structure disposed on a substrate including a thin film transistor (TFT), a passivation layer, and a pixel electrode is provided. The TFT includes a gate, a dielectric layer, a channel layer, and a source/drain sequentially disposed on the substrate. The source/drain is disposed on a portion of the channel layer and has a semiconductor layer, a barrier layer and a metal layer. The barrier layer is disposed on a portion of the semiconductor layer. The metal layer is disposed on the barrier layer. The barrier layer is in contact with the semiconductor layer and the metal layer. Both of the metal layer and the barrier layer are positioned within a projection area of the semiconductor layer. The passivation layer covers the TFT and the dielectric layer and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.

Abstract translation: 设置在包括薄膜晶体管（TFT），钝化层和像素电极的基板上的像素结构。 TFT包括顺序地设置在基板上的栅极，电介质层，沟道层和源极/漏极。 源极/漏极设置在沟道层的一部分上并具有半导体层，势垒层和金属层。 阻挡层设置在半导体层的一部分上。 金属层设置在阻挡层上。 阻挡层与半导体层和金属层接触。 金属层和阻挡层都位于半导体层的投影区域内。 钝化层覆盖TFT和电介质层，并且具有暴露源极/漏极的第一开口。 像素电极通过第一开口与TFT电连接。

公开(公告)号：US07535050B2

公开(公告)日：2009-05-19

申请号：US11272683

申请日：2005-11-15

Applicant: Chih-Ping Chung ,  Chun-Nan Lin ,  Chung-Yi Chen ,  Hung-Kwei Liao

Inventor： Chih-Ping Chung ,  Chun-Nan Lin ,  Chung-Yi Chen ,  Hung-Kwei Liao

IPC: H01L29/94

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.

Abstract translation: 描述包括多个存储器单元的存储器结构。 每个存储单元包括衬底，浅沟槽隔离，间隔物，隧道氧化物和浮动栅极。 衬底中的浅沟槽隔离用于限定有源区。 间隔物位于浅沟槽隔离物的侧壁处，并且高于浅沟槽隔离。 隧道氧化物在有源区上。 浮动栅极在隧道氧化物上。

公开(公告)号：US20090057668A1

公开(公告)日：2009-03-05

申请号：US12115855

申请日：2008-05-06

Applicant: Po-Lin Chen ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Kuo-Yuan Tu

Inventor： Po-Lin Chen ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Kuo-Yuan Tu

IPC: H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/458 ,  H01L27/124 ,  H01L29/41733

Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

Abstract translation: 提供了一种显示元件及其制造方法。 该方法包括以下步骤：在衬底上形成具有栅极的第一图案化导电层和其上的电介质层; 在所述电介质层上形成图案化的半导体层，其中所述图案化半导体层具有沟道区，源极和漏极，并且其中所述源极和漏极位于所述沟道区的相对侧上; 选择性地沉积仅包裹图案化半导体层的阻挡层; 在阻挡层上和源极和漏极之上形成第二图案化导电层。 在通过该方法制造的显示元件中，阻挡层仅包裹图案化的半导体层。

公开(公告)号：US07251706B2

公开(公告)日：2007-07-31

申请号：US11308243

申请日：2006-03-14

Applicant: Yung-Chun Lei ,  Chun-Nan Lin

Inventor： Yung-Chun Lei ,  Chun-Nan Lin

IPC: G06F12/00

CPC classification number: G06F8/65

Abstract: A processing system connected to an apparatus includes a non-volatile memory (NVM) for storing firmware needed by the processing system; and an NVM control interface capable of writing and reading data stored in the NVM; wherein the NVM control interface reads a previous piece of data being already written into the NVM prior to a current piece of data and transmits the previous piece of data to the apparatus for comparison with original data that was previously written into the NVM, and the NVM control interface writes the current piece of data into the NVM.

Abstract translation: 连接到装置的处理系统包括用于存储处理系统所需的固件的非易失性存储器（NVM） 以及能够写入和读取存储在NVM中的数据的NVM控制接口; 其中NVM控制接口在当前数据片段之前读取已经写入NVM中的先前数据块，并将先前的数据发送到装置以便与先前写入NVM的原始数据进行比较，并且NVM 控制接口将当前数据写入NVM。