公开(公告)号：US5119481A

公开(公告)日：1992-06-02

申请号：US696291

申请日：1991-04-26

Applicant: Steven J. Frank ,  Henry Burkhardt, III ,  Frederick D. Weber

Inventor： Steven J. Frank ,  Henry Burkhardt, III ,  Frederick D. Weber

IPC: G06F15/173 ,  H04L12/433

CPC classification number: H04L12/433 ,  G06F15/17337

Abstract: A digital data processing apparatus includes a shift-register bus that transfers packets of digital information. The bus has a plurality of digital storage and transfer stages connected in series in a ring configuration. A plurality of processing cells, each including at least a memory element, are connected in a ring configuration through the bus, with each cell being in communication with an associated subset of stages of the bus. At least one processing cell includes a cell interconnect that performs at least one of modifying, extracting, replicating and transferring a packet based on an association, if any, between a datum identified in that packet and one or more data stored in said associated memory element. The cell interconnect responds to applied digital clock cycle signals for simultaneously transferring at least a selected packet through successive stages of the bus at a rate responsive to the digital clock cycle rate, while performing the modifying, extracting, replicating and transferring operation.

Abstract translation: 数字数据处理装置包括传送数字信息包的移位寄存器总线。 该总线具有以环形配置串联连接的多个数字存储和传送级。 每个包括至少一个存储器元件的多个处理单元通过总线以环形配置连接，每个单元与总线的相关分级子集通信。 至少一个处理单元包括单元互连，其执行基于在该分组中识别的数据与存储在所述相关联的存储器元件中的一个或多个数据之间的关联（如果有的话）修改，提取，复制和传送分组中的至少一个 。 小区互连响应所应用的数字时钟周期信号，用于在执行修改，提取，复制和传送操作的同时以响应于数字时钟周期速率的速率在总线的连续级中同时传送至少一个选定分组。

公开(公告)号：US5055999A

公开(公告)日：1991-10-08

申请号：US136930

申请日：1987-12-22

Applicant: Steven J. Frank ,  Henry Burkhardt, III ,  Linda O. Lee ,  Nathan Goodman ,  Benson I. Margulies ,  Frederick D. Weber

Inventor： Steven J. Frank ,  Henry Burkhardt, III ,  Linda O. Lee ,  Nathan Goodman ,  Benson I. Margulies ,  Frederick D. Weber

IPC: G06F15/177 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F11/00 ,  G06F11/07 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  H04L12/46 ,  H04L12/56

CPC classification number: G06F9/5016 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0766 ,  G06F11/0772 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0833 ,  G06F12/10 ,  G06F12/1018 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/468 ,  G06F9/52 ,  H04L12/4637 ,  H04L45/04 ,  G06F12/126 ,  G06F2212/272

Abstract: A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.