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    Register bus multiprocessor system with shift
    7.
    发明授权
    Register bus multiprocessor system with shift 失效
    寄存器总线多处理器系统

    公开(公告)号：US5119481A

    公开(公告)日：1992-06-02

    申请号：US696291

    申请日：1991-04-26

    申请人： Steven J. Frank ,  Henry Burkhardt, III ,  Frederick D. Weber

    发明人： Steven J. Frank ,  Henry Burkhardt, III ,  Frederick D. Weber

    IPC分类号： G06F15/173 ,  H04L12/433

    CPC分类号： H04L12/433 ,  G06F15/17337

    摘要： A digital data processing apparatus includes a shift-register bus that transfers packets of digital information. The bus has a plurality of digital storage and transfer stages connected in series in a ring configuration. A plurality of processing cells, each including at least a memory element, are connected in a ring configuration through the bus, with each cell being in communication with an associated subset of stages of the bus. At least one processing cell includes a cell interconnect that performs at least one of modifying, extracting, replicating and transferring a packet based on an association, if any, between a datum identified in that packet and one or more data stored in said associated memory element. The cell interconnect responds to applied digital clock cycle signals for simultaneously transferring at least a selected packet through successive stages of the bus at a rate responsive to the digital clock cycle rate, while performing the modifying, extracting, replicating and transferring operation.

    摘要翻译： 数字数据处理装置包括传送数字信息包的移位寄存器总线。 该总线具有以环形配置串联连接的多个数字存储和传送级。 每个包括至少一个存储器元件的多个处理单元通过总线以环形配置连接，每个单元与总线的相关分级子集通信。 至少一个处理单元包括单元互连，其执行基于在该分组中识别的数据与存储在所述相关联的存储器元件中的一个或多个数据之间的关联（如果有的话）修改，提取，复制和传送分组中的至少一个 。 小区互连响应所应用的数字时钟周期信号，用于在执行修改，提取，复制和传送操作的同时以响应于数字时钟周期速率的速率在总线的连续级中同时传送至少一个选定分组。

    Computer system with processor cache that stores remote cache presence information
    9.
    发明授权
    Computer system with processor cache that stores remote cache presence information 有权
    具有处理器缓存的计算机系统，用于存储远程缓存存在信息

    公开(公告)号：US07096323B1

    公开(公告)日：2006-08-22

    申请号：US10256970

    申请日：2002-09-27

    申请人： Patrick Conway ,  Frederick D. Weber

    发明人： Patrick Conway ,  Frederick D. Weber

    IPC分类号： G06F13/14

    CPC分类号： G06F12/082 ,  G06F2212/2515 ,  Y02D10/13

    摘要： A computer system with a processor cache that stores remote cache presence information. In one embodiment, a plurality of presence vectors are stored to indicate whether particular blocks of data mapped to another node are being remotely cached. Rather than storing the presence vectors in a dedicated storage, the remote cache presence vectors may be stored in designated locations of a cache memory subsystem, such as an L2 cache, associated with a processor core. For example, a designated way of the cache memory subsystem may be allocated for storing remote cache presence vectors, while the remaining ways of the cache are used to store normal processor data. New data blocks may be remotely cached in response to evictions from the cache memory subsystem. In yet a further embodiment, additional entries of the cache memory subsystem may be used for storing directory entries to filter probe command and response traffic.

    摘要翻译： 具有存储远程缓存存在信息的处理器高速缓存的计算机系统。 在一个实施例中，存储多个存在向量以指示映射到另一节点的特定数据块是否被远程高速缓存。 而不是将存在向量存储在专用存储器中，远程高速缓存存在向量可以存储在与处理器核心相关联的高速缓冲存储器子系统（例如L 2高速缓存）的指定位置。 例如，缓存存储器子系统的指定方式可被分配用于存储远程高速缓存存在向量，而高速缓存的剩余方式用于存储正常的处理器数据。 响应于来自高速缓冲存储器子系统的驱逐，可以远程高速缓存新的数据块。 在又一个实施例中，高速缓存存储器子系统的附加条目可以用于存储目录条目以过滤探测命令和响应流量。

    Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria
    10.
    发明授权
    Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria 有权
    根据标准优化多管道可执行和特定管道可执行指令的分配到执行管道

    公开(公告)号：US06370637B1

    公开(公告)日：2002-04-09

    申请号：US09370789

    申请日：1999-08-05

    申请人： Stephan G. Meier ,  Norbert Juffa ,  Frederick D. Weber ,  Stuart F. Oberman

    发明人： Stephan G. Meier ,  Norbert Juffa ,  Frederick D. Weber ,  Stuart F. Oberman

    IPC分类号： G06F938

    CPC分类号： G06F9/30032 ,  G06F9/30192 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

    摘要： A microprocessor with a floating point unit configured to efficiently allocate multi-pipeline executable instructions is disclosed. Multi-pipeline executable instructions are instructions that are not forced to execute in a particular type of execution pipe. For example, junk ops are multi-pipeline executable. A junk op is an instruction that is executed at an early stage of the floating point unit's pipeline (e.g., during register rename), but still passes through an execution pipeline for exception checking. Junk ops are not limited to a particular execution pipeline, but instead may pass through any of the microprocessor's execution pipelines in the floating point unit. Multi-pipeline executable instructions are allocated on a per-clock cycle basis using a number of different criteria. For example, the allocation may vary depending upon the number of multi-pipeline executable instructions received by the floating point unit in a single clock cycle.

    摘要翻译： 公开了一种具有配置成有效地分配多流水线可执行指令的浮点单元的微处理器。 多管道可执行指令是不强制在特定类型执行管道中执行的指令。 例如，垃圾操作是多管道可执行的。 垃圾操作是在浮点单元的流水线的早期执行的指令（例如，在寄存器重命名期间），但是仍然通过用于异常检查的执行管线。 垃圾操作不限于特定的执行管道，而是可以通过浮点单元中的任何一个微处理器的执行流水线。 使用许多不同的标准，在每个时钟周期的基础上分配多流水线可执行指令。 例如，分配可以根据浮点单元在单个时钟周期中接收的多流水线可执行指令的数量而变化。