公开(公告)号：US06526502B1

公开(公告)日：2003-02-25

申请号：US09690371

申请日：2000-12-16

申请人： Gerard M. Col ,  G. Glenn Henry ,  Dinesh K. Jain

发明人： Gerard M. Col ,  G. Glenn Henry ,  Dinesh K. Jain

IPC分类号： G06F940

CPC分类号： G06F9/3861 ,  G06F9/3842 ,  G06F9/3848

摘要： An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively updates global branch history information based on the prediction of a first branch instruction so that the predictor can predict the outcome of a second branch instruction following closely in the pipeline with the benefit of the first prediction. This improves the prediction accuracy where the first branch has not been resolved prior to the time when the second prediction is ready to be made. If the first prediction turns out to be incorrect, the global branch history is restored from a previously saved copy and updated with the first branch instruction's actual outcome.

摘要翻译： 提供了一种通过提高条件分支指令的预测精度来提高微处理器性能的装置和方法。 动态分支预测器基于第一分支指令的预测来推测性地更新全局分支历史信息，使得预测器可以预测第二分支指令的结果，紧随其后的第一预测的益处。 这提高了在第二预测准备好之前第一分支尚未被解析的预测精度。 如果第一个预测结果不正确，则全局分支历史将从先前保存的副本中恢复，并以第一个分支指令的实际结果进行更新。

公开(公告)号：US06338136B1

公开(公告)日：2002-01-08

申请号：US09313908

申请日：1999-05-18

申请人： Gerard M. Col ,  Rodney E. Hooker

发明人： Gerard M. Col ,  Rodney E. Hooker

IPC分类号： G06F9302

CPC分类号： G06F9/3806 ,  G06F9/3017 ,  G06F9/3861

摘要： An apparatus and method are provided for executing a compare-and-jump operation in a pipeline microprocessor. Typically, the compare-and-jump operation is specified by two micro instructions. The first micro instruction, an ALU micro instruction, directs the microprocessor to perform an ALU operation, resulting in update of a flags register. The second micro instruction, a conditional jump micro instruction, directs the microprocessor to examine the flags register and to branch program control to a target address if a prescribed condition is met. The apparatus has a jump combiner that detects the ALU micro instruction and the conditional jump micro instruction in a micro instruction queue. The jump combiner indicates the prescribed condition for the conditional branch in a field of the ALU micro instruction, and then deletes the conditional jump micro instruction from the queue. The apparatus also has execution logic that performs the ALU operation, generates the result, and updates the flags register. The apparatus also has store logic that receives the generated result and examines the flags register as prescribed by the field of the single ALU micro instruction.

摘要翻译： 提供了一种用于在流水线微处理器中执行比较和跳转操作的装置和方法。 通常，比较和跳转操作由两个微指令指定。 第一个微指令ALU微指令指示微处理器执行ALU操作，导致更新标志寄存器。 如果满足规定的条件，则第二微指令是条件跳转微指令，指示微处理器检查标志寄存器并将程序控制分支到目标地址。 该装置具有跳转组合器，其检测微指令队列中的ALU微指令和条件跳转微指令。 跳转组合器在ALU微指令的字段中指示条件分支的规定条件，然后从队列中删除条件跳转微指令。 该装置还具有执行ALU操作的执行逻辑，生成结果，并更新标志寄存器。 该装置还具有接收生成结果的存储逻辑，并根据单个ALU微指令的字段来规定检查标志寄存器。

公开(公告)号：US09378019B2

公开(公告)日：2016-06-28

申请号：US14007077

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30174 ,  G06F9/30189

摘要： A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.

摘要翻译： 微处理器指令转换器将条件加载指令转换成至少两个微指令。 无序执行管线执行微指令。 为了执行第一微指令，执行单元从寄存器堆的源寄存器接收源操作数，并使用源操作数响应地生成第一结果。 为了执行微指令，执行单元接收目的地寄存器的先前值和第一结果，并响应于从第一结果指定的存储器位置读取数据，并且如果满足条件则提供作为数据的第二结果， 这是以前的目标寄存器值，如果没有。 目的地寄存器的先前值包括通过执行作为目的地寄存器相对于第二微指令的最新的有序先前的写入器的微指令而产生的结果。

公开(公告)号：US08880854B2

公开(公告)日：2014-11-04

申请号：US12369132

申请日：2009-02-11

申请人： Rodney E. Hooker ,  Gerard M. Col ,  Terry Parks

发明人： Rodney E. Hooker ,  Gerard M. Col ,  Terry Parks

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30076 ,  G06F9/3013 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842

摘要： An out-of-order execution microprocessor executes an architectural segment register-loading instruction that instructs the microprocessor to load a new value into an architectural segment register of the microprocessor. A comparator compares the new value specified by the architectural segment register-loading instruction with a current contents of the architectural segment register. A control unit causes to be re-executed using the new value all instructions in the microprocessor that used the current architectural segment register contents as a source operand and that are newer in program order than the architectural segment register-loading instruction whenever the comparator indicates the new value does not equal the current contents. An instruction scheduler retrieves the current contents and issues for execution instructions that use the retrieved current contents, even though the instructions are newer in program order than the register-loading instruction and the register-loading instruction has not yet written the new value to the architectural segment register.

摘要翻译： 无序执行微处理器执行体系结构段寄存器加载指令，其指示微处理器将新值加载到微处理器的架构段寄存器中。 比较器将结构化段寄存器加载指令指定的新值与架构段寄存器的当前内容进行比较。 控制单元导致使用新值将微处理器中的所有指令重新执行，该指令使用当前的体系结构段寄存器内容作为源操作数，并且只要比较器指示结构段寄存器加载指令，则程序顺序比结构化段寄存器加载指令更新 新值不等于当前内容。 指令调度器检索使用所检索的当前内容的执行指令的当前内容和问题，即使指令在程序顺序中比寄存器加载指令更新，并且寄存器加载指令尚未将新值写入架构 段寄存器。

公开(公告)号：US20140013089A1

公开(公告)日：2014-01-09

申请号：US14007077

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30174 ,  G06F9/30189

摘要： A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.

摘要翻译： 微处理器指令转换器将条件加载指令转换成至少两个微指令。 无序执行管线执行微指令。 为了执行第一微指令，执行单元从寄存器堆的源寄存器接收源操作数，并使用源操作数响应地生成第一结果。 为了执行微指令，执行单元接收目的地寄存器的先前值和第一结果，并响应于从第一结果指定的存储器位置读取数据，并且如果满足条件则提供作为数据的第二结果， 这是以前的目标寄存器值，如果没有。 目的地寄存器的先前值包括通过执行作为目的地寄存器相对于第二微指令的最新的有序先前的写入器的微指令而产生的结果。

公开(公告)号：US20120260071A1

公开(公告)日：2012-10-11

申请号：US13333631

申请日：2011-12-21

申请人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/345 ,  G06F9/315

CPC分类号： G06F9/30189 ,  G06F9/30072 ,  G06F9/30123 ,  G06F9/30174

摘要： An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register.

摘要翻译： 架构指令指示微处理器对第一和第二源操作数执行操作以产生结果，并且只有在体系结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。 硬件指令翻译器将架构指令转换为第一和第二微指令。 为了执行第一微指令，执行流水线对源操作数执行操作以生成结果，确定架构条件标志是否满足条件，并更新非架构指示符以指示架构条件标志是否满足条件。 为了执行第一微指令，如果由第一微指令更新的非架构指示符指示架构条件标志满足条件，则用结果更新目的寄存器; 否则，它将使用目标寄存器的当前值更新目标寄存器。

公开(公告)号：US07937561B2

公开(公告)日：2011-05-03

申请号：US12062028

申请日：2008-04-03

申请人： Gerard M. Col ,  Terry Parks

发明人： Gerard M. Col ,  Terry Parks

IPC分类号： G06F9/30

CPC分类号： G06F9/30109 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A microprocessor processes a macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register. An instruction translator translates the macroinstruction into a merge microinstruction that specifies an N-bit first source register, an 8-bit second source register, and an N-bit destination register to receive an N-bit result. The N-bit first source register and the N-bit destination register are the N-bit architected general purpose register. An execution unit receives the merge microinstruction and responsively generates the N-bit result to be subsequently written to the N-bit architected general purpose register even though the macroinstruction only instructs the microprocessor to write the 8-bit result into the lower 8 bits of the N-bit architected general purpose register. Specifically, the execution unit directs the 8-bit result into the lower 8 bits of the N-bit result and directs the upper N-8 bits of the N-bit first source register into corresponding upper N-8 bits of the N-bit result.

摘要翻译： 微处理器处理宏指令，指示微处理器将8位结果写入N位结构化通用寄存器的低8位。 指令转换器将宏指令转换成合并微指令，其指定N位第一源寄​​存器，8位第二源寄存器和N位目的寄存器以接收N位结果。 N位第一源寄​​存器和N位目标寄存器是N位架构的通用寄存器。 执行单元接收合并微指令，并且响应地生成随后写入N位构造的通用寄存器的N位结果，即使宏指令仅指示微处理器将8位结果写入到低位8位 N位架构通用寄存器。 具体地，执行单元将8位结果引导到N位结果的低8位，并将N位第一源寄​​存器的上N-8位导入N位的相应高N-8位 结果。

公开(公告)号：US20110060943A1

公开(公告)日：2011-03-10

申请号：US12793821

申请日：2010-06-04

申请人： G. Glenn Henry ,  Gerard M. Col ,  Timothy A. Elliott ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Timothy A. Elliott ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F11/14

CPC分类号： G06F9/3865 ,  G06F9/3001 ,  G06F9/30025

摘要： A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.

摘要翻译： 微处理器包括被配置为接收其指令和操作数并执行指令的多个执行单元。 指令调度器向执行单元发出指令并选择指令操作数的源。 执行单元中的至少一个检测其中一个指令的操作数之一是反正态操作数，响应于检测到该反正态操作数而产生指示需要重播的指示，并将该反正态操作数提供给指令调度器 对正反操作数进行检测的响应，而不是对正常操作数进行归一化。 指令调度器响应于该指示来对归一化操作数进行归一化，并且当指令被重放时，使归一化操作数而不是反正态操作数提供给执行单元。

公开(公告)号：US20100131742A1

公开(公告)日：2010-05-27

申请号：US12277409

申请日：2008-11-25

申请人： Gerard M. Col ,  Brent Bean ,  Bryan Wayne Pogor

发明人： Gerard M. Col ,  Brent Bean ,  Bryan Wayne Pogor

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3865 ,  G06F9/3867

摘要： A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instruction or a non-excepting type instruction. The excepting type instruction is capable of causing the microprocessor to take an exception after being issued to the execution unit, wherein the non-excepting type instruction is incapable of causing the microprocessor to take an exception after being issued. A retire unit makes a determination that an instruction is the oldest instruction in the microprocessor and that the instruction is ready to update the architectural state of the microprocessor with its result. The retire unit makes the determination before the execution unit outputs the result of the non-excepting type instruction, wherein the retire unit makes the determination after the execution unit outputs the result of the excepting type instruction.

摘要翻译： 一种微处理器，用于通过相对较小的订单指令退出缓冲区来改善无序超标量执行单元利用率。 多个执行单元各自计算指令结果。 该指令是异常类型指令或非除外类型指令。 除了类型指令能够使微处理器在发布到执行单元之后发生异常，其中非排除型指令不能使微处理器在发布之后发生异常。 退出单元确定指令是微处理器中最早的指令，并且该指令已准备好更新其结果为微处理器的架构状态。 退出单元在执行单元输出非除外类型指令的结果之前进行确定，其中退出单元在执行单元输出除外类型指令的结果之后进行确定。

公开(公告)号：US07185182B2

公开(公告)日：2007-02-27

申请号：US10771630

申请日：2004-02-04

申请人： Gerard M. Col

发明人： Gerard M. Col

IPC分类号： G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/3863

摘要： An apparatus and method for providing early instruction results is disclosed. Early execution logic, comprising an enhanced address generator located in an address generation stage of the microprocessor pipeline, receives input operands and generates early results of instructions reaching the address stage prior to final execution units (in lower pipeline stages) generating final results of the instruction for updating an architected register file. The early execution logic is configured to execute only a subset of the instructions in the microprocessor instruction set. The early results are invalid if the instruction is not in the subset. An early register file corresponding to the architected register file stores the early results and also provides the early results to the early execution logic as input operands. The generated early results are invalid if any input operands are invalid. Early status flags accumulated from the early results enable selective early execution of conditional instructions.

摘要翻译： 公开了一种用于提供早期指令结果的装置和方法。 早期执行逻辑包括位于微处理器流水线的地址生成阶段中的增强地址生成器，在最终执行单元（在较低流水线级）生成指令的最终结果之前，接收输入操作数并产生到达地址级的早期指令结果 用于更新架构化的寄存器文件。 早期执行逻辑被配置为仅执行微处理器指令集中的指令的子集。 如果指令不在子集中，则早期结果无效。 对应于架构化寄存器文件的早期寄存器文件存储早期结果，并且将早期结果提供给早期执行逻辑作为输入操作数。 如果任何输入操作数无效，生成的早期结果将无效。 从早期结果积累的早期状态标志可以有选择地早期执行条件指令。