公开(公告)号：US20240419023A1

公开(公告)日：2024-12-19

申请号：US18209680

申请日：2023-06-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02F1/035

Abstract: Photonics chip structures including an edge coupler and a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a substrate, an edge coupler on the substrate, and a layer including a portion that has an overlapping relationship with the edge coupler. The layer comprises a material that exhibits an electric-field-induced Pockels effect.

公开(公告)号：US20240402421A1

公开(公告)日：2024-12-05

申请号：US18802210

申请日：2024-08-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Thomas Houghton ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/30 ,  G02B6/42 ,  G02B6/43

Abstract: A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.

公开(公告)号：US12158442B2

公开(公告)日：2024-12-03

申请号：US17929404

申请日：2022-09-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu

IPC: G01N27/22

Abstract: An integrated circuit (IC) structure includes a moisture barrier about active circuitry. A capacitor is entirely inside the moisture barrier. The capacitor has a breakdown voltage. A moisture detector is configured to apply an increasing voltage ramp to the capacitor up to a maximum voltage less than the breakdown voltage of the capacitor. In response to determining that a current hump exists in a test current-voltage response curve of the capacitor to the increasing voltage ramp, the detector transmits a signal to the active circuitry to indicate a presence of moisture in the IC structure. The moisture detector is accurate and sensitive to moisture ingress, which provides more time for remedial action. The detector is non-destructive and can be used in a final IC product.

公开(公告)号：US20240395932A1

公开(公告)日：2024-11-28

申请号：US18322212

申请日：2023-05-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： John L. LEMON ,  Hong YU ,  Haiting WANG ,  Hui ZHAN

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wraparound gate structure and methods of manufacture. The structure includes: a channel region comprising semiconductor material; an isolation structure surrounding the channel region; a divot within the isolation structure; and a gate structure comprising gate material within the divot and surrounding the channel region.

公开(公告)号：US12148702B2

公开(公告)日：2024-11-19

申请号：US17879574

申请日：2022-08-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/02 ,  H01L27/092 ,  H01L29/08 ,  H01L27/118

Abstract: A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.

公开(公告)号：US20240380400A1

公开(公告)日：2024-11-14

申请号：US18313427

申请日：2023-05-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Venu Gopal Reddy Ara ,  Devesh Dwivedi

IPC: H03K19/0185

Abstract: Embodiments of the disclosure provide a customizable logic cells and related methods to form the same. A structure of the disclosure includes a first pair of complementary transistors connected in series between a first voltage node and a second voltage node. Each transistor of the first pair includes a gate coupled to a first input node. A second pair of complementary transistors is connected in series between the first voltage node and the second voltage node in an opposite orientation from the first pair of complementary transistors. Each transistor of the second pair includes a gate coupled to a second input node. An output line is coupled to a first electrical connection between the first pair complementary transistors and a second electrical connection between the second pair of complementary transistors.

公开(公告)号：US20240377583A1

公开(公告)日：2024-11-14

申请号：US18196796

申请日：2023-05-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/122 ,  G02B6/13

Abstract: Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a photodetector including a pad and a semiconductor layer on the pad, a first waveguide core including a tapered section adjacent to a sidewall of the semiconductor layer, and a second waveguide core including a curved section adjacent to the sidewall of the semiconductor layer. The curved section includes a plurality of segments, and the tapered section of the first waveguide core is overlapped by at least one of the plurality of segments in the curved section of the second waveguide core.

公开(公告)号：US12142686B2

公开(公告)日：2024-11-12

申请号：US17330780

申请日：2021-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Uzma Rana ,  Steven M. Shank ,  Mark D. Levy

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.

公开(公告)号：US20240369760A1

公开(公告)日：2024-11-07

申请号：US18141753

申请日：2023-05-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Arpan Dasgupta ,  Zahidur Chowdhury ,  Takako Hirokawa ,  Vaishnavi Karra ,  Norman Robson

IPC: G02B6/12 ,  G02B6/136 ,  H04N5/33

Abstract: Structures including a light source and an edge coupler, and methods of forming and using such structures. The structure comprises a semiconductor substrate and a back-end-of-line stack on the semiconductor substrate. The back-end-of-line stack includes a first dielectric layer, a first plurality of metal features in the first dielectric layer, a second dielectric layer on the first dielectric layer, and a second plurality of metal features in the second dielectric layer. The second plurality of metal features have a non-overlapping relationship with the first plurality of metal features. The structure further comprises an edge coupler adjacent to the first plurality of metal features and the second plurality of metal features.

公开(公告)号：US20240361545A1

公开(公告)日：2024-10-31

申请号：US18307151

申请日：2023-04-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu ,  Erdem Kaltalioglu

IPC: G02B6/42

CPC classification number: G02B6/4248 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/564

Abstract: A structure includes an integrated circuit (IC) chip including a substrate. An input/output (I/O) opening extends inwardly from an exterior surface of the IC chip. A metal finger structure protrudes partly into the I/O opening, and outer surfaces of the metal finger structure are covered by a moisture barrier. The metal finger structure may provide stress-relief by removing attacking surfaces for stress in the I/O opening and/or otherwise reduces stress, such as film stresses, to reduce damage to the moisture barrier and improve reliability compared to conventional devices.