公开(公告)号：US20110272784A1

公开(公告)日：2011-11-10

申请号：US13185873

申请日：2011-07-19

Applicant: Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

Inventor： Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

IPC: H01L29/92

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894

Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.

Abstract translation: 提出了具有高方位圆柱形电容器的半导体器件及其制造方法。 高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。 半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。 单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。 存储节点氧化物位于半导体衬底上的周边区域中。 导电层涂覆保护环孔。 在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。 覆盖氧化物部分地填充导电层的一部分。 间隙填充膜填充在导电层的其余部分。

公开(公告)号：US07723183B2

公开(公告)日：2010-05-25

申请号：US12499248

申请日：2009-07-08

Applicant: Ho Jin Cho ,  Cheol Hwan Park ,  Jae Soo Kim ,  Dong Kyun Lee

Inventor： Ho Jin Cho ,  Cheol Hwan Park ,  Jae Soo Kim ,  Dong Kyun Lee

IPC: H01L21/02

CPC classification number: H01L28/65 ,  H01L27/10852 ,  H01L28/91

Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.

Abstract translation: 通过在具有存储节点接触插塞的半导体衬底上形成缓冲氧化物层，蚀刻停止层和模具绝缘层来制造电容器。 蚀刻模具绝缘层和蚀刻停止层，以在存储节点接触插塞的上部形成孔。 在包括孔的模具绝缘层上沉积渐缩层。 锥形层和缓冲氧化物层被回蚀刻，使得锥形层仅保留在蚀刻孔的上端部。 在剩余的锥形层上形成在蚀刻孔上的金属储存节点层。 去除模具绝缘层和剩余的锥形层以形成具有锥形上端的圆柱形存储节点。 在存储节点上形成介电层和板状节点。

公开(公告)号：US20090275186A1

公开(公告)日：2009-11-05

申请号：US12265759

申请日：2008-11-06

Applicant: Cheol Hwan PARK ,  Ho Jin CHO ,  Jae Soo KIM ,  Dong Kyun LEE

Inventor： Cheol Hwan PARK ,  Ho Jin CHO ,  Jae Soo KIM ,  Dong Kyun LEE

IPC: H01L21/02

CPC classification number: H01L28/91

Abstract: Forming a capacitor of a semiconductor device includes forming an interlayer dielectric having holes over a semiconductor substrate. A conductive layer is then formed on surfaces of the holes and on the upper surface of the interlayer dielectric. A silicon-containing conductive layer is formed by flowing a silicon source gas for the semiconductor substrate formed with the conductive layer, so that silicon atoms can penetrate into the conductive layer. The silicon-containing conductive layer prevents etchant from infiltrating the interlayer dielectric below the silicon-containing conductive layer.

Abstract translation: 形成半导体器件的电容器包括在半导体衬底上形成具有孔的层间电介质。 然后在孔的表面和层间电介质的上表面上形成导电层。 通过使形成有导电层的半导体衬底的硅源气体流动而形成含硅导电层，使得硅原子能够渗透到导电层中。 含硅导电层防止蚀刻剂渗透到含硅导电层之下的层间电介质。

公开(公告)号：US07463476B2

公开(公告)日：2008-12-09

申请号：US11148057

申请日：2005-06-07

Applicant: Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

Inventor： Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

IPC: H01G4/06

CPC classification number: B82Y10/00 ,  H01G4/005 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract translation: 提供了一种具有纳米管的电容器及其制造方法。 所述电容器包括：下电极，其包括图案化导电层和形成在所述图案化导电层上的多个纳米管，所述多个纳米管不需要使用催化剂层; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。 该方法包括以下步骤：形成用于形成下电极的导电层; 在不使用催化剂层的情况下形成包括形成在所述导电层上的多个纳米管的纳米管阵列; 在纳米管阵列上形成介电层; 以及在所述电介质层上形成上电极。

公开(公告)号：US20080157093A1

公开(公告)日：2008-07-03

申请号：US11779093

申请日：2007-07-17

Applicant: Ho Jin CHO ,  Cheol Hwan PARK ,  Jae Soo KIM ,  Dong Kyun LEE

Inventor： Ho Jin CHO ,  Cheol Hwan PARK ,  Jae Soo KIM ,  Dong Kyun LEE

IPC: H01L29/12 ,  H01L21/20

CPC classification number: H01L28/65 ,  H01L27/10852 ,  H01L28/91

Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.

Abstract translation: 通过在具有存储节点接触插塞的半导体衬底上形成缓冲氧化物层，蚀刻停止层和模具绝缘层来制造电容器。 蚀刻模具绝缘层和蚀刻停止层，以在存储节点接触插塞的上部形成孔。 在包括孔的模具绝缘层上沉积渐缩层。 锥形层和缓冲氧化物层被回蚀刻，使得锥形层仅保留在蚀刻孔的上端部。 在剩余的锥形层上形成在蚀刻孔上的金属储存节点层。 去除模具绝缘层和剩余的锥形层以形成具有锥形上端的圆柱形存储节点。 在存储节点上形成介电层和板状节点。

公开(公告)号：US07208419B2

公开(公告)日：2007-04-24

申请号：US10738397

申请日：2003-12-17

Applicant: Seung Woo Jin ,  Bong Soo Kim ,  Ho Jin Cho

Inventor： Seung Woo Jin ,  Bong Soo Kim ,  Ho Jin Cho

IPC: H01L21/302

CPC classification number: H01L21/823418 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823468

Abstract: The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: forming a gate line on a semiconductor substrate; forming a buffer layer and a spacer nitride film on the entire surface of the substrate including the gate line; selectively etching the buffer layer and the spacer nitride film in such a manner that they remain on both sides of the gate line; performing an ion implantation process using the remaining buffer layer and spacer nitride film as a barrier film to form junction regions in the semiconductor substrate at both sides of the gate line; forming an interlayer insulating film on the entire upper portion of the resulting substrate; selectively removing the interlayer insulating film to form contact holes exposing the upper surface of the junction regions; and forming contact plugs in the contact holes.

Abstract translation: 本发明涉及半导体器件的制造方法。 该方法包括以下步骤：在半导体衬底上形成栅极线; 在包括栅极线的基板的整个表面上形成缓冲层和间隔氮化物膜; 选择性地蚀刻缓冲层和间隔氮化物膜，使得它们保留在栅极线的两侧; 使用剩余缓冲层和间隔氮化物膜作为阻挡膜进行离子注入工艺，以在栅极线的两侧在半导体衬底中形成结区域; 在所得基板的整个上部形成层间绝缘膜; 选择性地去除层间绝缘膜以形成暴露接合区域的上表面的接触孔; 并在接触孔中形成接触塞。

公开(公告)号：US20060221548A1

公开(公告)日：2006-10-05

申请号：US11148057

申请日：2005-06-07

Applicant: Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

Inventor： Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

IPC: H01G4/228

CPC classification number: B82Y10/00 ,  H01G4/005 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

公开(公告)号：US06800567B2

公开(公告)日：2004-10-05

申请号：US10226028

申请日：2002-08-22

Applicant: Ho Jin Cho

Inventor： Ho Jin Cho

IPC: H01L2131

CPC classification number: H01L21/02271 ,  H01L21/02197 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/31691 ,  H01L21/318

Abstract: A method for forming a polyatomic layer with a mixed deposition method consisting of an atomic layer deposition method (ALD) and a chemical vapor deposition method. The mixed deposition method can be adopted to form a polyatomic high dielectric layer, such as BST or STO. Accordingly, it is possible to form a polyatomic high dielectric layer having a uniform composition distribution, and thereby also having a high dielectric characteristic and a low leakage current characteristic.

Abstract translation: 一种由原子层沉积法（ALD）和化学气相沉积法组成的混合沉积法形成多原子层的方法。 可以采用混合沉积法形成诸如BST或STO的多原子高介电层。 因此，可以形成具有均匀组成分布的多原子高电介质层，从而也具有高介电特性和低漏电流特性。

公开(公告)号：US6054332A

公开(公告)日：2000-04-25

申请号：US414236

申请日：1999-10-07

Applicant: Ho Jin Cho

Inventor： Ho Jin Cho

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/00

CPC classification number: H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: The present invention provides a method for fabricating a capacitor of a semiconductor memory device to improve the characteristic of step coverage during depositing upper electrode, and simultaneously to prevent impurities remained between upper electrode and high dielectric layer.The method for fabricating capacitor of a semiconductor memory device comprises the steps of: forming an intermetal insulating layer having a contact hole for exposing a junction region on a semiconductor substrate provided with the junction region; forming a contact plug within the contact hole; forming a barrier layer on the contact plug and on the adjoining intermetal insulating layer; forming a lower electrode so as to surround the barrier layer; forming a high dielectric layer on the intermetal insulating layer formed on the lower electrode; forming an upper electrode on the high dielectric layer according to the MOCVD method; and crystallizing the lower electrode, the high dielectric layer and the upper electrode, wherein in the step of forming the upper electrode, a step of supplying precursors used for forming the upper electrode for a selected time, and a step of interrupting the supply of precursors for a selected time are repeated at least one time.

Abstract translation: 本发明提供了一种用于制造半导体存储器件的电容器的方法，以改善在沉积上电极期间阶梯覆盖的特性，同时防止上电极和高电介质层之间残留的杂质。 制造半导体存储器件的电容器的方法包括以下步骤：形成具有接触孔的金属间绝缘层，用于暴露具有接合区域的半导体衬底上的接合区域; 在所述接触孔内形成接触塞; 在接触插塞和相邻的金属间绝缘层上形成阻挡层; 形成下部电极以包围阻挡层; 在形成在下电极上的金属间绝缘层上形成高介电层; 根据MOCVD方法在高电介质层上形成上电极; 以及使下电极，高电介质层和上电极结晶，其中在形成上电极的步骤中，提供用于选择时间形成上电极的前体的步骤，以及中断前体供给步骤 至少一次重复选定的时间。