公开(公告)号：US07638407B2

公开(公告)日：2009-12-29

申请号：US12265759

申请日：2008-11-06

Applicant: Cheol Hwan Park ,  Ho Jin Cho ,  Jae Soo Kim ,  Dong Kyun Lee

Inventor： Cheol Hwan Park ,  Ho Jin Cho ,  Jae Soo Kim ,  Dong Kyun Lee

IPC: H01L21/20

CPC classification number: H01L28/91

Abstract: Forming a capacitor of a semiconductor device includes forming an interlayer dielectric having holes over a semiconductor substrate. A conductive layer is then formed on surfaces of the holes and on the upper surface of the interlayer dielectric. A silicon-containing conductive layer is formed by flowing a silicon source gas for the semiconductor substrate formed with the conductive layer, so that silicon atoms can penetrate into the conductive layer. The silicon-containing conductive layer prevents etchant from infiltrating the interlayer dielectric below the silicon-containing conductive layer.

Abstract translation: 形成半导体器件的电容器包括在半导体衬底上形成具有孔的层间电介质。 然后在孔的表面和层间电介质的上表面上形成导电层。 通过使形成有导电层的半导体衬底的硅源气体流动而形成含硅导电层，使得硅原子能够渗透到导电层中。 含硅导电层防止蚀刻剂渗透到含硅导电层之下的层间电介质。

公开(公告)号：US07576383B2

公开(公告)日：2009-08-18

申请号：US11779093

申请日：2007-07-17

Applicant: Ho Jin Cho ,  Cheol Hwan Park ,  Jae Soo Kim ,  Dong Kyun Lee

Inventor： Ho Jin Cho ,  Cheol Hwan Park ,  Jae Soo Kim ,  Dong Kyun Lee

IPC: H01L27/108

CPC classification number: H01L28/65 ,  H01L27/10852 ,  H01L28/91

Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.

Abstract translation: 通过在具有存储节点接触插塞的半导体衬底上形成缓冲氧化物层，蚀刻停止层和模具绝缘层来制造电容器。 蚀刻模具绝缘层和蚀刻停止层，以在存储节点接触插塞的上部形成孔。 在包括孔的模具绝缘层上沉积渐缩层。 锥形层和缓冲氧化物层被回蚀刻，使得锥形层仅保留在蚀刻孔的上端部。 在剩余的锥形层上形成在蚀刻孔上的金属储存节点层。 去除模具绝缘层和剩余的锥形层以形成具有锥形上端的圆柱形存储节点。 在存储节点上形成介电层和板状节点。

公开(公告)号：US20070264770A1

公开(公告)日：2007-11-15

申请号：US11618796

申请日：2006-12-30

Applicant: Keum Bum Lee ,  Hai Won Kim ,  Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Dong Su Park

Inventor： Keum Bum Lee ,  Hai Won Kim ,  Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Dong Su Park

IPC: H01L21/8242 ,  H01L29/92

CPC classification number: H01L21/3141 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/0234 ,  H01L27/10852 ,  H01L28/91

Abstract: A method for forming a capacitor includes forming a concave mold over a semiconductor substrate. A storage node is formed on the concave mold. A dielectric layer including a zirconium oxide (ZrO2) layer is deposited over the storage node at a first temperature. A radical pile-up treatment on the dielectric layer is performed in an atmosphere including radicals at a second temperature higher than the first temperature to induce crystallization of the dielectric layer. A plate node is formed over the dielectric layer.

Abstract translation: 形成电容器的方法包括在半导体衬底上形成凹模。 存储节点形成在凹模上。 包含氧化锆（ZrO 2）层的电介质层在第一温度下沉积在存储节点上。 在包括自由基的气氛中，在高于第一温度的第二温度下进行介电层上的自由基堆积处理，以诱导电介质层的结晶。 在该电介质层上形成一个平板节点。

公开(公告)号：US06841925B2

公开(公告)日：2005-01-11

申请号：US10323079

申请日：2002-12-19

Applicant: Song Geun Lee ,  Ho Jin Cho ,  Kwang Yun Choi

Inventor： Song Geun Lee ,  Ho Jin Cho ,  Kwang Yun Choi

IPC: H01J29/76 ,  H01J29/82 ,  H01J29/70 ,  H04N5/655

CPC classification number: H01J29/76 ,  H01J29/826

Abstract: Disclosed is a deflection yoke comprising: a fastening band of a ring shape assembled on an outer periphery of a neck portion in a coil separator by a fixing manner, provided for being extended and contracted; a pair of flanges bent and extended from both ends of the fastening band, on which a through hole is formed; a yoke clamp for generating fastening force by tightening of a bolt for passing through a pair of through holes, then being tightened by a nut; a bending portion projected on an outer side along the periphery of the fastening band, whose object contact plane for coming in contact with an outer periphery of the neck portion is divided into at least two or more.

Abstract translation: 本发明公开了一种偏转线圈，其特征在于，包括：通过固定方式组装在线圈分离器的颈部的外周上的环状的紧固带，用于延伸和收缩; 从形成有通孔的紧固带的两端弯曲并延伸的一对凸缘; 用于通过拧紧用于穿过一对通孔的螺栓产生紧固力的轭夹，然后由螺母紧固; 沿着紧固带的外周突出的外侧的弯曲部分，其与颈部的外周接触的物体接触面被划分为至少两个以上。

公开(公告)号：US20130016239A1

公开(公告)日：2013-01-17

申请号：US13415285

申请日：2012-03-08

Applicant: Jung Uk CHO ,  Seung Yong LEE ,  Sung Hyun CHO ,  Shi Hwa LEE ,  Young Su MOON ,  Ho Jin CHO

Inventor： Jung Uk CHO ,  Seung Yong LEE ,  Sung Hyun CHO ,  Shi Hwa LEE ,  Young Su MOON ,  Ho Jin CHO

IPC: H04N5/228 ,  G06K9/40

CPC classification number: H04N5/23277

Abstract: A method and apparatus for removing a non-uniform motion blur using a multi-frame may estimate non-uniform motion blur information using a multi-frame including a non-uniform motion blur, and may remove the non-uniform motion blur using the estimated non-uniform motion blur and the multi-frame. The apparatus may also obtain more accurate non-uniform motion blur information by iteratively performing the estimation of the non-uniform motion blur information, and the removal of the non-uniform motion blur.

Abstract translation: 使用多帧去除不均匀运动模糊的方法和装置可以使用包括非均匀运动模糊的多帧估计不均匀运动模糊信息，并且可以使用所估计的运动模糊消除非均匀运动模糊 非均匀运动模糊和多帧。 该装置还可以通过迭代地执行非均匀运动模糊信息的估计和去除非均匀运动模糊来获得更精确的不均匀运动模糊信息。

公开(公告)号：US07906419B2

公开(公告)日：2011-03-15

申请号：US12275332

申请日：2008-11-21

Applicant: Jae Soo Kim ,  Cheol Hwan Park ,  Ho Jin Cho

Inventor： Jae Soo Kim ,  Cheol Hwan Park ,  Ho Jin Cho

IPC: H01L21/3205

CPC classification number: H01L21/268 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

Abstract: A laser annealing method for manufacturing a semiconductor device is presented. The method includes at least two forming steps and one annealing step. The first forming steps includes forming gates on a semiconductor substrate. The second forming step includes forming an insulation layer on the semiconductor substrate and on the gates. The annealing step includes annealing the insulation layer using electromagnetic radiation emitted from a laser.

Abstract translation: 提出了一种用于制造半导体器件的激光退火方法。 该方法包括至少两个形成步骤和一个退火步骤。 第一形成步骤包括在半导体衬底上形成栅极。 第二形成步骤包括在半导体衬底上和栅极上形成绝缘层。 退火步骤包括使用从激光发射的电磁辐射对绝缘层进行退火。

公开(公告)号：US20110024874A1

公开(公告)日：2011-02-03

申请号：US12647621

申请日：2009-12-28

Applicant: Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

Inventor： Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: A semiconductor device having a three-dimensional capacitor and a method for manufacturing the same is presented. The semiconductor device may have lower electrodes, a buffer layer, a dielectric layer, and an upper electrode. The lower electrodes are formed over a semiconductor substrate. The buffer layer is formed on sidewalls of the lower electrodes. The dielectric layer and an upper electrode are formed over semiconductor substrate including over the lower electrodes and the buffer layer. Accordingly, sufficient space between the lower electrodes can be secured. Furthermore, the lower electrodes can be each formed of a ruthenium layer and a titanium nitride layer and configured to have a pillar form. The dielectric layer may be composed of titanium dioxide.

Abstract translation: 本发明提供一种具有三维电容器的半导体器件及其制造方法。 半导体器件可以具有下电极，缓冲层，电介质层和上电极。 下电极形成在半导体衬底上。 缓冲层形成在下电极的侧壁上。 电介质层和上电极形成在包括在下电极和缓冲层之上的半导体衬底之上。 因此，可以确保下部电极之间的足够的空间。 此外，下电极可以由钌层和氮化钛层形成，并且被构造成具有柱状。 电介质层可以由二氧化钛构成。

公开(公告)号：US20090140385A1

公开(公告)日：2009-06-04

申请号：US12288880

申请日：2008-10-24

Applicant: Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

Inventor： Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

IPC: H01L29/00

CPC classification number: B82Y10/00 ,  H01G4/005 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract translation: 提供了一种具有纳米管的电容器及其制造方法。 所述电容器包括：下电极，其包括图案化导电层和形成在所述图案化导电层上的多个纳米管，所述多个纳米管不需要使用催化剂层; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。 该方法包括以下步骤：形成用于形成下电极的导电层; 在不使用催化剂层的情况下形成包括形成在所述导电层上的多个纳米管的纳米管阵列; 在纳米管阵列上形成介电层; 以及在所述电介质层上形成上电极。

公开(公告)号：US20080194090A1

公开(公告)日：2008-08-14

申请号：US11966185

申请日：2007-12-28

Applicant: Gyu Dong CHO ,  Ho Jin CHO ,  Hyun Jung KIM

Inventor： Gyu Dong CHO ,  Ho Jin CHO ,  Hyun Jung KIM

IPC: H01L21/283

CPC classification number: H01L29/66621 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/3143

Abstract: A method for manufacturing a semiconductor device for use in avoiding unwanted oxidation along exposed surfaces and for use in relieving etching damage is presented. The method includes step of forming sequentially a gate insulation layer, a polysilicon layer, a barrier layer, a metallic layer and a hard mask layer over a semiconductor substrate. The method also includes a step of etching the hard mask layer, the metallic layer, the barrier layer, the polysilicon layer and the gate insulation layer to form a gate. The method also includes a nitrifying step which uses a free radical is assisted chemical vapor deposition (RACVD) nitrifying process on surfaces of the layers forming the gate and a surface of the semiconductor substrate. The method also includes a step of subsequently performing a reoxidation process to the semiconductor substrate resultant that the RACVD nitrifying process is performed.

Abstract translation: 本发明提供一种制造半导体器件的方法，该半导体器件用于避免暴露表面的不必要的氧化并用于缓解蚀刻损伤。 该方法包括在半导体衬底上依次形成栅极绝缘层，多晶硅层，势垒层，金属层和硬掩模层的步骤。 该方法还包括蚀刻硬掩模层，金属层，势垒层，多晶硅层和栅极绝缘层以形成栅极的步骤。 该方法还包括在形成栅极和半导体衬底的表面的表面上使用自由基辅助化学气相沉积（RACVD）硝化过程的硝化步骤。 该方法还包括随后对半导体衬底的再氧化过程产生RACVD硝化过程的步骤。

公开(公告)号：US20080070398A1

公开(公告)日：2008-03-20

申请号：US11758512

申请日：2007-06-05

Applicant: Dong Su Park ,  Ho Jin Cho ,  Keum Bum Lee ,  Su Jin Chae ,  Cheol-Hwan Park

Inventor： Dong Su Park ,  Ho Jin Cho ,  Keum Bum Lee ,  Su Jin Chae ,  Cheol-Hwan Park

IPC: H01L23/525

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an antireflection layer containing either silicon or aluminum sequentially from bottom to top on the interlayer insulating layer. The method also includes patterning the antireflection layer, the first metal layer, and the barrier metal layer to form a first metal interconnection. The method also includes forming a fuse with the same material and structure as those of the first metal interconnection while forming the first metal interconnection. The method further includes forming an inter-metal dielectric layer on the first metal interconnection and the fuse, forming a second metal interconnection on the inter-metal dielectric layer, forming a passivation layer on the second metal interconnection, and forming a fuse box in the passivation layer.

Abstract translation: 这里公开了一种制造具有金属保险丝的半导体器件的方法。 该方法包括在半导体衬底上形成平板电极，在平板电极上形成层间绝缘层，从底部依次形成含有硅或铝的阻挡金属层，第一金属层和含有硅或铝的抗反射层， 顶层在层间绝缘层上。 该方法还包括图案化抗反射层，第一金属层和阻挡金属层以形成第一金属互连。 该方法还包括形成具有与第一金属互连相同的材料和结构的熔丝，同时形成第一金属互连。 该方法还包括在第一金属互连和熔丝上形成金属间电介质层，在金属间绝缘层上形成第二金属互连，在第二金属互连上形成钝化层，并在第 钝化层。