公开(公告)号：US20130146893A1

公开(公告)日：2013-06-13

申请号：US13760496

申请日：2013-02-06

Applicant: Kong-Beng THEI ,  Jiun-Lei Jerry YU ,  Chun Lin TSAI ,  Hsiao-Chin TUAN ,  Alex KALNITSKY

Inventor： Kong-Beng THEI ,  Jiun-Lei Jerry YU ,  Chun Lin TSAI ,  Hsiao-Chin TUAN ,  Alex KALNITSKY

IPC: H01L27/06

CPC classification number: H01L27/0617 ,  H01L21/26506 ,  H01L21/8258 ,  H01L27/085 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate.

Abstract translation: 提供了在硅衬底上具有GaN基器件和Si基器件的硅衬底。 硅衬底包括SiC结晶区上的GaN基器件。 在硅衬底中形成SiC晶体区域。 硅衬底还包括在硅区域上的基于Si的器件，并且硅区域位于硅衬底上的SiC晶体区域的旁边。

公开(公告)号：US20120061681A1

公开(公告)日：2012-03-15

申请号：US12881505

申请日：2010-09-14

Applicant: Kong-Beng THEI ,  Jiun-Lei Jerry YU ,  Chun Lin TSAI ,  Hsiao-Chin TUAN ,  Alex KALNITSKY

Inventor： Kong-Beng THEI ,  Jiun-Lei Jerry YU ,  Chun Lin TSAI ,  Hsiao-Chin TUAN ,  Alex KALNITSKY

IPC: H01L29/12 ,  H01L21/265

CPC classification number: H01L27/0617 ,  H01L21/26506 ,  H01L21/8258 ,  H01L27/085 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions.

Abstract translation: 在上述Si衬底上形成SiC结晶区的机理能够在同一衬底上形成GaN和GaN基器件的集成。 通过将碳注入到Si衬底的区域中，然后使衬底退火来形成SiC晶体区域。 在形成SiC晶体区域期间，使用注入停止层来覆盖Si器件区域。

公开(公告)号：US20110298045A1

公开(公告)日：2011-12-08

申请号：US12792025

申请日：2010-06-02

Applicant: Alex KALNITSKY ,  Hsiao-Chin TUAN ,  Kuo-Ming WU ,  Wei Tsung HUANG

Inventor： Alex KALNITSKY ,  Hsiao-Chin TUAN ,  Kuo-Ming WU ,  Wei Tsung HUANG

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7827 ,  H01L21/26586 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: The process methods and structures mentioned above for creating a trench MOSFET enables self-aligned contacts to be formed to allow decreasing pitch size for trench MOSFET. The self-aligned contacts are formed by etching exposed silicon areas without using lithographical mask and alignment. As a result, the allowance for alignment can be saved and the pitch size can be decreased.

Abstract translation: 上述用于产生沟槽MOSFET的工艺方法和结构使得能够形成自对准触点，以允许减小沟槽MOSFET的间距尺寸。 通过蚀刻暴露的硅区域而不使用光刻掩模和对准来形成自对准触点。 结果，可以节省对准的余量，并且可以减小间距尺寸。

公开(公告)号：US5270243A

公开(公告)日：1993-12-14

申请号：US35232

申请日：1993-03-22

Applicant: Hsiao-Chin Tuan ,  Yih-Fang Liu

Inventor： Hsiao-Chin Tuan ,  Yih-Fang Liu

IPC: H01L21/8242 ,  H01L21/70

CPC classification number: H01L27/10852

Abstract: A method and resulting structure for defining a dielectric layer thickness and etching openings having a desired aspect ratio through said dielectric layer covering regions in the peripheral circuits of a DRAM integrated circuit to be electrically contacted in a semiconductor wafer is described. The DRAM integrated circuit including the peripheral circuits to be electrically contacted is provide in the semiconductor wafer. A first conductive polysilicon layer is formed over said DRAM integrated circuit and the layer is patterned to leave the layer over the peripheral circuits. A first interlevel dielectric layer is formed over the polysilicon layer which has been patterned. A second conductive polysilicon layer is formed over the first interlevel dielectric layer and patterned to leave the layer over areas other than the peripheral circuits. The first interlevel dielectric layer and first polysilicon layer thereunder are masked and etched to remove the first interlevel dielectric layer and first polysilicon layer from all the peripheral circuits. A second interlevel dielectric layer is formed over the exposed second conductive polysilicon layer, first interlevel dielectric and semiconductor wafer. The openings having a desired aspect ratio are etched through said second interlevel dielectric layer.

Abstract translation: 描述了一种用于限定介电层厚度的方法和结果，并且通过在半导体晶片中电接触的DRAM集成电路的外围电路中的所述介电层覆盖区域蚀刻具有期望的纵横比的开口。 在半导体晶片中提供包括要电接触的外围电路的DRAM集成电路。 在所述DRAM集成电路上形成第一导电多晶硅层，并且对该层进行图案化以将层留在外围电路上。 在图案化的多晶硅层上形成第一层间电介质层。 第二导电多晶硅层形成在第一层间电介质层之上，并被图案化以将层留在外围电路以外的区域上。 对其之下的第一层间介质层和第一多晶硅层进行掩模蚀刻以从所有外围电路去除第一层间介质层和第一多晶硅层。 在暴露的第二导电多晶硅层，第一层间介质和半导体晶片之上形成第二层间电介质层。 通过所述第二层间介质层蚀刻具有期望的纵横比的开口。