公开(公告)号：US09111905B2

公开(公告)日：2015-08-18

申请号：US13434431

申请日：2012-03-29

Applicant: Fu-Wei Yao ,  Chen-Ju Yu ,  King-Yuen Wong ,  Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Chun Lin Tsai

Inventor： Fu-Wei Yao ,  Chen-Ju Yu ,  King-Yuen Wong ,  Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/778 ,  H01L29/08

CPC classification number: H01L29/452 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/28575 ,  H01L29/0843 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

Abstract translation: 高电子迁移率晶体管（HEMT）包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 自杀剂源特征和自杀物排放特征通过第二III-V化合物层与第一III-V化合物层接触。 栅极电极设置在第一III-V化合物层的一部分之间，位于自对准硅化物源特征和自对准硅化物漏极特征之间。

公开(公告)号：US08786050B2

公开(公告)日：2014-07-22

申请号：US13100714

申请日：2011-05-04

Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L21/02

CPC classification number: H01L28/20 ,  H01L27/0207 ,  H01L27/0802

Abstract: Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

Abstract translation: 提供高压半导体器件。 半导体器件包括位于衬底中的相对掺杂的掺杂阱。 半导体器件包括位于掺杂阱上的电介质结构。 邻近电介质结构的掺杂阱的一部分具有比掺杂阱的剩余部分更高的掺杂浓度。 半导体器件包括位于电介质结构上的细长多晶硅结构。 细长多晶硅结构具有长度L.与电介质结构相邻的掺杂阱的部分电耦合到细长多晶硅结构的段，其远离细长多晶硅结构的中点远离所测量的预定距离 细长多晶硅结构。 预定距离在从大约0 * L到大约0.1 * L的范围内。

公开(公告)号：US08704279B2

公开(公告)日：2014-04-22

申请号：US13481462

申请日：2012-05-25

Applicant: Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

Inventor： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L29/80

CPC classification number: H01L29/7832 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H03K17/223

Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Abstract translation: 一种器件包括掩埋阱区和第一导电性的第一HVW区，以及位于第一HVW区上的绝缘区。 第一导电类型的漏极区域设置在绝缘区域的第一侧和第一HVW区域的顶表面区域中。 与第一导电类型相反的第二导电类型的第一阱区和第二阱区在绝缘区的第二侧上。 第一导电类型的第二HVW区域设置在第一和第二阱区域之间，其中第二HVW区域连接到掩埋阱区域。 第一导电类型的源极区域位于第二HVW区域的顶表面区域中，其中源极区域，漏极区域和掩埋阱区域形成JFET。

公开(公告)号：US08624322B1

公开(公告)日：2014-01-07

申请号：US13551262

申请日：2012-07-17

Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Jen-Hao Yeh ,  Chun-Wei Hsu

Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Jen-Hao Yeh ,  Chun-Wei Hsu

IPC: H01L23/62 ,  H01L21/8234

CPC classification number: H01L27/0629

Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.

Abstract translation: 提供高压半导体器件。 高电压半导体器件包括具有栅极，源极和漏极的晶体管。 源极和漏极形成在掺杂衬底中并且由衬底的漂移区域分离。 栅极形成在漂移区域上以及源极和漏极之间。 晶体管被配置为处理至少几百伏特的高电压条件。 高电压半导体器件包括在晶体管的源极和漏极之间形成的电介质结构。 电介质结构突出进出基板。 电介质结构的不同部分具有不均匀的厚度。 高电压半导体器件包括在电介质结构上形成的电阻器。 电阻器具有大致均匀间隔开的多个绕组段。

公开(公告)号：US20130313617A1

公开(公告)日：2013-11-28

申请号：US13481462

申请日：2012-05-25

Applicant: Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

Inventor： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L29/80

CPC classification number: H01L29/7832 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H03K17/223

Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Abstract translation: 一种器件包括掩埋阱区和第一导电性的第一HVW区，以及位于第一HVW区上的绝缘区。 第一导电类型的漏极区域设置在绝缘区域的第一侧和第一HVW区域的顶表面区域中。 与第一导电类型相反的第二导电类型的第一阱区和第二阱区在绝缘区的第二侧上。 第一导电类型的第二HVW区域设置在第一和第二阱区域之间，其中第二HVW区域连接到掩埋阱区域。 第一导电类型的源极区域位于第二HVW区域的顶表面区域中，其中源极区域，漏极区域和掩埋阱区域形成JFET。

公开(公告)号：US08502326B2

公开(公告)日：2013-08-06

申请号：US12888113

申请日：2010-09-22

Applicant: Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chien-Chih Chou ,  Chun-Lin Tsai

Inventor： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chien-Chih Chou ,  Chun-Lin Tsai

IPC: H01L21/02 ,  H01L21/3205

CPC classification number: H01L21/823462 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

Abstract: An integrated circuit structure includes a semiconductor substrate and a high-voltage metal-oxide-semiconductor (HVMOS) device, which includes a first high-voltage well (HVW) region of a first conductivity type in the semiconductor substrate; a drain region of a second conductivity type opposite the first conductivity type in the semiconductor substrate and spaced apart from the first HVW region; a gate dielectric with at least a portion directly over the first HVW region; and a gate electrode over the gate dielectric. The gate dielectric includes a bottom gate oxide region; and a silicon nitride region over the bottom gate oxide region.

Abstract translation: 集成电路结构包括半导体衬底和高电压金属氧化物半导体（HVMOS）器件，其包括在半导体衬底中的第一导电类型的第一高电压阱（HVW）区域; 在所述半导体衬底中与所述第一HVW区间隔开的第二导电类型的与所述第一导电类型相反的漏极区; 栅极电介质，其具有直接在所述第一HVW区域上的至少一部分; 以及在栅极电介质上的栅电极。 栅极电介质包括底部栅极氧化物区域; 以及在底部栅极氧化物区域上方的氮化硅区域。

公开(公告)号：US20120193637A1

公开(公告)日：2012-08-02

申请号：US13049699

申请日：2011-03-16

Applicant: Alexander Kalnitsky ,  Chih-Wen Hsiung ,  Chun Lin Tsai

Inventor： Alexander Kalnitsky ,  Chih-Wen Hsiung ,  Chun Lin Tsai

IPC: H01L29/778 ,  H01L21/338 ,  H01L29/22

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42316 ,  H01L29/66143 ,  H01L29/7787

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; and a gate stack disposed on the AlGaN layer. The gate stack includes a III-V compound n-type doped layer; a III-V compound p-type doped layer adjacent the III-V compound n-type doped layer; and a metal layer formed over the III-V compound p-type doped layer and the III-V compound n-type doped layer.

Abstract translation: 本公开提供了一种半导体结构。 半导体结构在衬底上包括氮化镓（GaN）层; 设置在GaN层上的氮化镓铝（AlGaN）层; 以及设置在AlGaN层上的栅极堆叠。 栅堆叠包括III-V族化合物n型掺杂层; 与III-V化合物n型掺杂层相邻的III-V族化合物p型掺杂层; 以及在III-V族化合物p型掺杂层和III-V族化合物n型掺杂层上形成的金属层。

公开(公告)号：US10014291B2

公开(公告)日：2018-07-03

申请号：US13760496

申请日：2013-02-06

Applicant: Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai ,  Hsiao-Chin Tuan ,  Alex Kalnitsky

Inventor： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai ,  Hsiao-Chin Tuan ,  Alex Kalnitsky

IPC: H01L29/15 ,  H01L27/06 ,  H01L21/8258 ,  H01L27/085 ,  H01L21/265

CPC classification number: H01L27/0617 ,  H01L21/26506 ,  H01L21/8258 ,  H01L27/085 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate.

公开(公告)号：US08803232B2

公开(公告)日：2014-08-12

申请号：US13186660

申请日：2011-07-20

Applicant: Ker Hsiao Huo ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng

Inventor： Ker Hsiao Huo ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/404 ,  H01L29/0607 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816

Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

Abstract translation: 横向DMOS晶体管设置有源极区，漏极区和导电栅。 漏极区域通过在导电栅极下方侵入的场氧化物与导电栅极横向分离。 横向DMOS晶体管可以形成为跑道状结构，其中导电栅极包括直线部分和弯曲部分并被源极区域包围。 布置在导电栅极和捕获的漏极之间是一层或多层次的层间电介质材料。 一组或多组隔离的导体引线形成在电介质层中或介质层上，并且可以设置在多个器件级。 隔离导电引线增加了横向DMOS晶体管的击穿电压，特别是在电场拥挤可能会降低击穿电压的弯曲区域中。

公开(公告)号：US08680616B2

公开(公告)日：2014-03-25

申请号：US12959538

申请日：2010-12-03

Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L21/00

CPC classification number: H01L29/7816 ,  H01L21/76202 ,  H01L27/0629 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/861

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括：漂移区，其具有形成在衬底中的第一掺杂极性; 掺杂的延伸区域形成在所述漂移区域中，并且具有与所述第一掺杂极性相反的第二掺杂极性，所述掺杂延伸区域包括横向延伸的部件; 在所述漂移区上形成的电介质结构，所述电介质结构通过所述漂移区的一部分与所述掺杂延伸区分离; 形成在电介质结构的一部分上的栅结构和掺杂延伸区的一部分; 以及具有第二掺杂极性的掺杂隔离区，所述掺杂隔离区至少部分地围绕所述漂移区和所述掺杂延伸区。