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    Multilayer insulated wire and transformer using the same
    31.
    发明授权
    Multilayer insulated wire and transformer using the same 有权
    多层绝缘电线和变压器使用相同

    公开(公告)号：US06525272B2

    公开(公告)日：2003-02-25

    申请号：US09768534

    申请日：2001-01-24

    Applicant: Atsushi Higashiura ,  Isamu Kobayashi ,  Atsushi Taba

    Inventor： Atsushi Higashiura ,  Isamu Kobayashi ,  Atsushi Taba

    IPC: H01B700

    CPC classification number: H01F27/323

    Abstract: A multilayer insulated wire which includes a conductor and two or more solderable, extruded insulating layers with which the conductor is coated. The first insulating layer nearest to the conductor includes a thermoplastic polyester elastomer resin and the outermost insulating layer is composed of a thermoplastic polyamide resin. A transformer in which the multilayer insulated wire is utilized.

    Abstract translation: 一种多层绝缘电线，其包括导体和两个或多个可焊接的挤出绝缘层，导体被涂覆在该绝缘层上。 最接近导体的第一绝缘层包括热塑性聚酯弹性体树脂，最外层绝缘层由热塑性聚酰胺树脂组成。 使用多层绝缘电线的变压器。

    Semiconductor device
    32.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06472929B2

    公开(公告)日：2002-10-29

    申请号：US09927371

    申请日：2001-08-13

    Applicant: Isamu Kobayashi ,  Yoshiharu Kato ,  Takahiro Yokoyama

    Inventor： Isamu Kobayashi ,  Yoshiharu Kato ,  Takahiro Yokoyama

    IPC: G05F110

    CPC classification number: G05F3/242

    Abstract: A semiconductor device which is capable of shutting off the influence of noise introduced into a reference voltage while preventing an increase in die size. The semiconductor device including a reference potential generator, first and second filter, and first and second input circuit. The reference potential generator generates a reference potential in accordance with a first power supply. The first filter is connected to the first power supply and filters the reference potential to generate a first filtered reference potential. The second filter is connected to a second power supply and filters the reference potential to generate a second filtered reference potential. The first input circuit is connected to the first power supply and receives the first filtered reference potential to generate a first predetermined voltage. The second input circuit is connected to the second power supply and receives the second filtered reference potential to generate a second predetermined voltage.

    Abstract translation: 一种半导体器件，其能够在阻止芯片尺寸增大的同时，切断引入参考电压的噪声的影响。 该半导体器件包括参考电位发生器，第一和第二滤波器以及第一和第二输入电路。 参考电位发生器根据第一电源产生参考电位。 第一滤波器连接到第一电源并对参考电位进行滤波以产生第一滤波参考电位。 第二滤波器连接到第二电源并对参考电势进行滤波以产生第二滤波参考电位。 第一输入电路连接到第一电源并且接收第一滤波参考电位以产生第一预定电压。 第二输入电路连接到第二电源并接收第二滤波参考电位以产生第二预定电压。

    Semiconductor gate array device
    34.
    发明授权
    Semiconductor gate array device 失效
    半导体门阵列器件

    公开(公告)号：US6160275A

    公开(公告)日：2000-12-12

    申请号：US692253

    申请日：1996-08-05

    Applicant: Yoji Nishio ,  Yasuo Kaminaga ,  Isamu Kobayashi ,  Yoshihiko Yamamoto ,  Nozomi Horino ,  Kousaku Hirose

    Inventor： Yoji Nishio ,  Yasuo Kaminaga ,  Isamu Kobayashi ,  Yoshihiko Yamamoto ,  Nozomi Horino ,  Kousaku Hirose

    IPC: H01L27/118 ,  H01L27/10

    CPC classification number: H01L27/11807

    Abstract: In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within the MOS channel width W of each MOS, that are connected to the GND power lines 51 and 53, or the Vcc power lines 50 and 52--are formed in the direction perpendicular to each of the power lines. Additionally, in order to present a semiconductor integrated device having a static type RAM that has realized with its simple structure a shortening of the memory cycle, a RAM is constructed by having memory cells, in which each is composed of a pair of transfer MOSFETs, which both of the MOSFETs are turned on during the write-in operation and one of the MOSFETs is turned on during the read-out operation, is located in between a complementary data line and an input/output node that has a complementary relationship with an information storage part comprised by a pair of inverter circuits in which the inputs and outputs are mutually cross-connected. By constructing in this way, it becomes possible to speed up the write-in operation with accuracy by having a complementary write-in signal received from a pair of the complementary lines during the read-out operation, and it becomes possible to obtain read-out signals rapidly and to prevent write-in errors caused by the pre-read-out potential of the data line because the information storage part is connected only to one of the data lines through one of the transfer gates during the read-out operation.

    Abstract translation: 为了呈现具有高存储密度和高速逻辑电路的主片式LSI的基本单元，基本单元由每对PMOS 1，NMOS 4，PMOS 7和NMOS 10组成，并且三个 接触孔 - 除了接触孔17之外，因为连接到GND电源线51和53或Vcc电源线50和52的每个MOS的MOS沟道宽度W内的接触孔形成在垂直方向上 到每个电力线。 此外，为了呈现具有通过其简单结构实现的具有简化结构的静态型RAM的半导体集成器件，缩短了存储器周期，RAM通过具有存储单元构成，其中每个存储单元由一对转移MOSFET组成， 其中两个MOSFET在写入操作期间导通，并且在读出操作期间MOSFET中的一个导通，位于互补数据线与具有互补关系的输入/输出节点之间 信息存储部分由输入和输出相互交叉连接的一对反相器电路组成。 通过以这种方式构造，可以通过在读出操作期间具有从一对互补线接收的互补写入信号来准确地加速写入操作，并且可以获得读取操作， 并且防止由于数据线的预读出电位引起的写入错误，因为信息存储部分在读出操作期间仅通过一个传输门连接到一条数据线。

    Semiconductor integrated circuit device
    35.
    发明授权
    Semiconductor integrated circuit device 失效

    公开(公告)号：US4905140A

    公开(公告)日：1990-02-27

    申请号：US96912

    申请日：1987-09-16

    Applicant: Yasuhiro Sakakibara ,  Isamu Kobayashi ,  Yoshinori Suzuki

    Inventor： Yasuhiro Sakakibara ,  Isamu Kobayashi ,  Yoshinori Suzuki

    IPC: G11C17/00 ,  G06F12/06 ,  G06F15/78 ,  G11C16/02

    CPC classification number: G06F12/0684

    Abstract: In a one-chip microcomputer, an EPROM is formed together with a ROM and RAM on one semiconductor substrate. Data such as fixed data necessary in the microcomputer can be changed by the use of the EPROM. In case data are to be written in the EPROM, an EPROM writer is used. This EPROM writer outputs write data to the EPROM and checks (or verifies) the data written in the EPROM immediately thereafter. If any error is detected, the subsequent data write is interrupted. In order to inhibit the unnecessary operation interruption in case the address designated by the EPROM writer comes out of the range of the EPROM, the checking (or verifying) data signal to be fed from the one-chip microcomputer to the EPROM writer is forcibly set at a level which indicates satisfactory operation of the EPROM.

    ELECTRONIC THERMOMETER
    40.
    发明申请
    ELECTRONIC THERMOMETER 失效
    电子温度计

    公开(公告)号：US20090074029A1

    公开(公告)日：2009-03-19

    申请号：US11909762

    申请日：2006-03-14

    Applicant: Tetsuya Yamamoto ,  Isamu Kobayashi

    Inventor： Tetsuya Yamamoto ,  Isamu Kobayashi

    IPC: G01K7/42

    CPC classification number: G01K7/42 ,  G01K13/002

    Abstract: An electronic thermometer includes a temperature sensing means for sensing a temperature of a part to be measured, and a prediction means for calculating an equilibrium temperature according to the temperature being sensed. The prediction means includes a parameter determination unit for calculating parameters of a prediction function having three parameters to obtain an equilibrium predicted temperature, and an equilibrium predicted temperature calculation means for calculating an equilibrium temperature during a period of the thermal equilibrium time, based on the parameters determined by the parameter determination unit. The parameter determination unit determines parameters held by the prediction function, based on three (or two) sensed temperatures and the measuring times thereof. According to the prediction function, the equilibrium temperature can be predicted with a small number of samplings, and the parameters are determined based on the sensed temperature and the measuring time of the sensed temperature. Consequently, the number of samplings to predict the equilibrium temperature is reduced, as well as solving a problem that the equilibrium temperature may be varied due to an external factor, individual difference, and the like.

    Abstract translation: 一种电子体温计包括：感测待测部件的温度的温度检测装置;以及根据感测温度计算平衡温度的预测装置。 预测装置包括：参数确定单元，用于计算具有三个参数以获得平衡预测温度的预测函数的参数;以及平衡预测温度计算装置，用于基于参数来计算热平衡时间段期间的平衡温度 由参数确定单元确定。 参数确定单元基于三（或两个）感测温度及其测量时间来确定由预测功能保持的参数。 根据预测函数，可以用少量采样预测平衡温度，并根据感测温度和检测温度的测量时间来确定参数。 因此，预测平衡温度的采样次数减少，并且解决了由于外部因素，个体差异等而使平衡温度可能变化的问题。

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