公开(公告)号：US08253470B2

公开(公告)日：2012-08-28

申请号：US12881434

申请日：2010-09-14

Applicant: Jan Mulder

Inventor： Jan Mulder

IPC: H03L5/00

CPC classification number: H03F3/45475 ,  H03F3/45192 ,  H03F3/45928 ,  H03F2203/45048 ,  H03F2203/45138 ,  H03F2203/45586 ,  H03M1/1023 ,  H03M1/165

Abstract: An apparatus, a method, and a system are provided to calibrate an offset in an amplifier. The apparatus can include an amplifier, a voltage control unit, a comparator, and a processing unit. The amplifier can have four terminals: a positive differential input (VIN+), a negative differential input (VIN−), a positive differential output (VOUT+), and a negative differential output (VOUT−). The voltage control unit can be configured to adjust a first voltage on VOUT+ and a second voltage on VOUT−. The comparator can be configured to compare the first voltage on VOUT+ to the second voltage on VOUT− when VIN+ and VIN− are coupled to a common voltage. Further, the processing unit can be configured to provide a control signal to the voltage control unit based on the comparison of the first and second voltages on VOUT+ and VOUT−, respectively.

Abstract translation: 提供了一种装置，方法和系统来校准放大器中的偏移。 该装置可以包括放大器，电压控制单元，比较器和处理单元。 放大器可以有四个端子：正差分输入（VIN +），负差分输入（VIN-），正差分输出（VOUT +）和负差分输出（VOUT-））。 电压控制单元可配置为调节VOUT +上的第一电压和VOUT-上的第二电压。 当VIN +和VIN-耦合到公共电压时，比较器可以配置为将VOUT +上的第一个电压与VOUT-上的第二个电压进行比较。 此外，处理单元可以被配置为基于VOUT +和VOUT-上的第一和第二电压的比较来向电压控制单元提供控制信号。

公开(公告)号：US20100162957A1

公开(公告)日：2010-07-01

申请号：US12601234

申请日：2008-05-21

Applicant: Adam Boyd ,  Victor Saywell ,  Jan Mulder ,  Olivier Feron ,  Johannes Käppeler

Inventor： Adam Boyd ,  Victor Saywell ,  Jan Mulder ,  Olivier Feron ,  Johannes Käppeler

IPC: C23C16/46 ,  C23C16/458

CPC classification number: C23C16/4583 ,  H01L21/68735 ,  H01L21/68757 ,  H01L21/68771

Abstract: The invention relates to a device for coating a plurality of substrates (3) which are regularly arranged on a bearing surface (2) of a susceptor (1) associated to a process chamber (14), wherein the bearing surface (2) forms abutment flanks (5) for the edge mounting of each substrate (3). In order to reduce the free susceptor surface to a minimum, it is proposed that the abutment flanks of the lateral walls (5) are formed by bases (4) which project from the bearing surface (2) and are separated at a distance from one another. Said bases are arranged on the corner points (10) of a honeycomb structure and have an outline essentially corresponding to an equilateral triangle with inwardly curved sides (5).

Abstract translation: 本发明涉及一种用于涂覆多个基板（3）的装置，其定期地布置在与处理室（14）相关联的基座（1）的支承表面（2）上，其中支承表面（2）形成支座 用于每个基板（3）的边缘安装的侧面（5）。 为了将自由基座表面最小化，提出侧壁（5）的邻接侧面由从轴承表面（2）突出的基部（4）形成，并且距离一个距离 另一个。 所述底座布置在蜂窝结构的角点（10）上，并且具有基本对应于具有向内弯曲侧面（5）的等边三角形的轮廓。

公开(公告)号：US07710184B2

公开(公告)日：2010-05-04

申请号：US11523694

申请日：2006-09-20

Applicant: Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward

IPC: H03K5/00

CPC classification number: H03H19/004

Abstract: The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.

Abstract translation: 本发明涉及信号处理电路，更具体地说，涉及开关电容器电路以及减少符号间干扰的方法。 提供了具有减小的符号间干扰效应的开关电容器电路，包括：电压源，第一电容器，第二电容器和至少一个开关，其被配置为以将第一电容器充电到第一电容器 电压，然后通过第二电容器放电，从而减少符号间干扰效应。

公开(公告)号：US07589655B2

公开(公告)日：2009-09-15

申请号：US12204482

申请日：2008-09-04

Applicant: Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

Inventor： Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

IPC: H03M1/66

CPC classification number: H03F3/45183 ,  H03F2203/45466

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The method includes identifying a phase control signal from an adjacent current cell preceding the particular current cell in time and logically ORing the phase control signal from the preceding cell with a phase control signal from the particular current cell.

Abstract translation: 提供了一种用于控制具有发射机的收发机中的电流特性的方法和系统。 该方法包括在时间上识别来自特定当前小区之前的相邻当前小区的相位控制信号，并且将来自前一小区的相位控制信号与来自特定当前小区的相位控制信号进行逻辑或运算。

公开(公告)号：US20080088493A1

公开(公告)日：2008-04-17

申请号：US11857417

申请日：2007-09-18

Applicant: Jan MULDER ,  Franciscus van der GOES ,  Jan WESTRA ,  Rudy van der PLASSCHE

Inventor： Jan MULDER ,  Franciscus van der GOES ,  Jan WESTRA ,  Rudy van der PLASSCHE

IPC: H03M1/66

CPC classification number: H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.

Abstract translation: 电压内插电路包括连接在地和电压输入端之间的电阻梯形电阻，并具有多个电阻器，电阻器之间具有电压抽头。 放大器（可选地）具有在其相应的第一端子和放大器的输入端连接在一起的第一和第二电容器。 第一多个开关将各个抽头连接到第一电容器的第二端子。 第二多个开关将各个抽头连接到第二电容器的第二端子。 通过控制第一和第二多个开关来内插输出电压。

公开(公告)号：US07271755B2

公开(公告)日：2007-09-18

申请号：US10926407

申请日：2004-08-26

Applicant: Jan Mulder ,  Franciscus Maria Leonardus van der Goes ,  Jan Westra ,  Rudy van der Plassche

Inventor： Jan Mulder ,  Franciscus Maria Leonardus van der Goes ,  Jan Westra ,  Rudy van der Plassche

IPC: H03M1/12 ,  H03M1/78 ,  G06F17/17

CPC classification number: H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.

Abstract translation: 电压内插电路包括连接在地和电压输入端之间的电阻梯形电阻，并具有多个电阻器，电阻器之间具有电压抽头。 放大器（可选地）具有在其相应的第一端子和放大器的输入端连接在一起的第一和第二电容器。 第一多个开关将各个抽头连接到第一电容器的第二端子。 第二多个开关将各个抽头连接到第二电容器的第二端子。 通过控制第一和第二多个开关来内插输出电压。

公开(公告)号：US07256725B2

公开(公告)日：2007-08-14

申请号：US11651454

申请日：2007-01-10

Applicant: Jan Mulder

Inventor： Jan Mulder

IPC: H03M1/12

CPC classification number: H03K17/04106 ,  H03F3/45183 ,  H03F3/45632 ,  H03F2203/45352 ,  H03F2203/45354 ,  H03F2203/45511 ,  H03M1/204 ,  H03M1/365

Abstract: An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.

公开(公告)号：US20070182476A1

公开(公告)日：2007-08-09

申请号：US11523694

申请日：2006-09-20

Applicant: Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward

IPC: G06G7/18

CPC classification number: H03H19/004

Abstract: The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.

Abstract translation: 本发明涉及信号处理电路，更具体地说，涉及开关电容器电路以及减少符号间干扰的方法。 提供了具有减小的符号间干扰效应的开关电容器电路，包括：电压源，第一电容器，第二电容器和至少一个开关，其被配置为以将第一电容器充电到第一电容器 电压，然后通过第二电容器放电，从而减少符号间干扰效应。

公开(公告)号：US20070109173A1

公开(公告)日：2007-05-17

申请号：US11651454

申请日：2007-01-10

Applicant: Jan Mulder

Inventor： Jan Mulder

IPC: H03M1/12

CPC classification number: H03K17/04106 ,  H03F3/45183 ,  H03F3/45632 ,  H03F2203/45352 ,  H03F2203/45354 ,  H03F2203/45511 ,  H03M1/204 ,  H03M1/365

Abstract: An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.

Abstract translation: 模数转换器包括输出多个参考电压的电阻梯形图和接收参考电压的粗略ADC和电压输入。 多个粗略比较器接收粗略ADC的输出。 开关矩阵接收粗略ADC的输出和参考电压。 开关矩阵输入用于选择至少两个电压子范围的多个控制信号。 精密ADC接收两个电压子范围和电压输入。 多个精细比较器接收精细ADC的输出。 编码器将粗略和精细比较器的输出转换为电压输入的数字表示。 电压子范围相邻。 每个控制信号包括用于控制相应的开关的多个控制线。 开关是场效应晶体管。

公开(公告)号：US07208980B2

公开(公告)日：2007-04-24

申请号：US11038386

申请日：2005-01-21

Applicant: Jan Mulder

Inventor： Jan Mulder

IPC: G01R19/00

CPC classification number: G01R19/16519 ,  G01R19/16557 ,  H03F3/45183 ,  H03F3/45632 ,  H03F2200/78 ,  H03F2203/45366 ,  H03F2203/45644 ,  H03M1/0607

Abstract: A differential comparator with reduced offset. The differential comparator includes a first transistor coupled to a first input current and a second transistor coupled to a second input current. The first and second transistors are biased as diodes during a reset phase to store an offset voltage on parasitic capacitances of the first and second transistors. The first and second transistors are connected together as a latch to provide an output during a latch phase. Drain currents of the first and the second transistors substantially equal the first and the second input currents, respectively, during the reset phase and at the beginning of the latch phase. During the latch phase, currents approximately twice as large as differential-mode signal currents provided by the first and the second input currents are provided to the first and the second transistors, respectively.

Abstract translation: 具有减小偏移的差分比较器。 差分比较器包括耦合到第一输入电流的第一晶体管和耦合到第二输入电流的第二晶体管。 第一和第二晶体管在复位阶段被偏置为二极管，以便在第一和第二晶体管的寄生电容上存储偏移电压。 第一和第二晶体管作为锁存器连接在一起以在锁存相位期间提供输出。 第一和第二晶体管的漏极电流分别在复位阶段期间和锁存相位开始时基本上等于第一和第二输入电流。 在锁存阶段期间，分别向第一和第二晶体管提供大约是由第一和第二输入电流提供的差分模式信号电流的两倍的电流。