公开(公告)号：US20090027947A1

公开(公告)日：2009-01-29

申请号：US11815415

申请日：2006-02-03

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C11/412 ,  G11C7/00 ,  G11C5/14

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/092

Abstract: In a reading operation, an off time and a reading time of a holding control transistor is controlled by a replica circuit, so that a read margin is enlarged. Furthermore, a high power source potential and a low power source potential of an SRAM memory cell are switched in reading and writing operations of the memory cell and in a data holding state by a power source potential switching portion. As a result, a write margin is enlarged, and a leakage current is reduced.

Abstract translation: 在读取操作中，由复制电路控制保持控制晶体管的关闭时间和读取时间，从而放大读取余量。 此外，SRAM存储单元的高电源电位和低电源电位在存储单元的读取和写入操作中被切换，并且在电源电位切换部分处于数据保持状态。 结果，写入裕度被放大，并且漏电流减小。

公开(公告)号：US20080128314A1

公开(公告)日：2008-06-05

申请号：US11885969

申请日：2006-03-10

Applicant: Koichi Takeda ,  Kenji Matsuda ,  Toshimitsu Terao ,  Tadaaki Inoue ,  Takashi Imagawa

Inventor： Koichi Takeda ,  Kenji Matsuda ,  Toshimitsu Terao ,  Tadaaki Inoue ,  Takashi Imagawa

IPC: A61J3/00 ,  A61K47/12 ,  B65D25/08 ,  A61K31/337

CPC classification number: A61K9/0019 ,  A61K9/1075 ,  A61K9/127 ,  A61K31/337

Abstract: The present invention provides a pharmaceutical composition which can permit a sparingly water-soluble drug substance to be solubilized or dispersed in a pharmaceutically allowable liquid medium (e.g., fat emulsion, etc.), characterized in that said pharmaceutical composition contains (a) a base (e.g., polyethylene glycol, etc.), (b) a sparingly water-soluble drug substance and (c) a fatty acid or its pharmaceutically allowable salt. The pharmaceutical composition can be mixed with a pharmaceutically allowable liquid medium to produce a pharmaceutical preparation for administration, such as an injectable solution, etc., wherein mixing can be performed for a shortened period of time and the sparingly water-soluble drug substance can be uniformly solubilized or dispersed in a liquid medium.

Abstract translation: 本发明提供一种药物组合物，其可以使微溶于水的药物物质溶解或分散在药学上可允许的液体培养基（例如脂肪乳液等）中，其特征在于所述药物组合物含有（a） （例如聚乙二醇等），（b）微溶水性药物和（c）脂肪酸或其药学上可允许的盐。 药物组合物可以与药学上可允许的液体培养基混合以制备用于施用的药物制剂，例如注射液等，其中混合可以缩短一段时间，并且微量水溶性药物可以是 均匀溶解或分散在液体介质中。

公开(公告)号：US20080031037A1

公开(公告)日：2008-02-07

申请号：US11793080

申请日：2005-12-16

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C11/412 ,  G11C11/41 ,  G11C7/10 ,  G11C11/00 ,  G11C7/00 ,  G11C11/34

CPC classification number: G11C11/412

Abstract: When an SRAM cell formed by six transistors is made finer and operated at a lower voltage, it does not operate stably. Because many transistors and control signals are required for stable operation, there is a problem that its component area is increased. An SRAM cell is formed by five transistors. The SRAM cell is formed by an inverter circuit (P1, N1) using a storage node V2 as an input and a storage node V1 as an output, a load transistor P2 connected between a power source VDD and the storage node V2 with using the storage node V1 as an input and the storage node V2 as an output, an access transistor N3 connected between a read bit line RBL and the storage node V1, and an access transistor N4 connected between a write bit line WBL and the storage node V2. When the access transistor N4 is controlled by a write word line WWL, the access transistor N4 can be used as holding control means and writing means for the memory cell, making it possible to obtain a semiconductor device capable of operating at a high speed with a small number of elements.

Abstract translation: 当由六个晶体管形成的SRAM单元更精细并且在较低电压下操作时，其不能稳定地运行。 由于需要许多晶体管和控制信号来稳定运行，所以存在其组件面积增大的问题。 SRAM单元由五个晶体管形成。 SRAM单元由使用存储节点V 2作为输入的反相器电路（P 1，N 1）和存储节点V 1作为输出形成，负载晶体管P 2连接在电源VDD与存储节点 V 2，使用存储节点V 1作为输入，存储节点V 2作为输出，连接在读位线RBL和存储节点V1之间的存取晶体管N 3和连接在存储节点V 2之间的存取晶体管N 4 写位线WBL和存储节点V 2。 当访问晶体管N 4由写入字线WWL控制时，存取晶体管N 4可以用作存储单元的保持控制装置和写入装置，使得可以获得能够高速运行的半导体器件 与少量元素。

公开(公告)号：US06922090B2

公开(公告)日：2005-07-26

申请号：US10094921

申请日：2002-03-12

Applicant: Koichi Takeda ,  Kimito Horie

Inventor： Koichi Takeda ,  Kimito Horie

IPC: G06F13/37 ,  G06F7/00 ,  H03K19/0175 ,  G11C7/00 ,  G06F1/12 ,  H03K19/096

CPC classification number: G06F7/00

Abstract: The present invention implements an asynchronous transition signaling circuit which can be applied to a bus arbitrator or the like. The OR gate holds a token (feedback signal S) as long as the device enabling signal Grant is output, even after the request event ReqIn is canceled, and as a result, the Muller C element with an inverter cancels the output of the response event AckOut. When the device request signal Req is not output, the feedback signal S passes through the AND gate, and the request event ReqOut is output from the AND gate. At the same time, the device enabling signal Grant is no longer output, and the loop comprised of the Muller C element with an inverter, the OR gate and the AND gate is canceled. As a result, the token (feedback signal S) is transferred to the next transition signaling circuit.

Abstract translation: 本发明实现了可应用于总线仲裁器等的异步转换信令电路。 即使在请求事件ReqIn被取消之后，或门输出令牌（反馈信号S），只要能够使能信号Grant被输出，结果，具有反相器的Muller C元件取消响应事件的输出 AckOut。 当不输出设备请求信号Req时，反馈信号S通过与门，并且请求事件ReqOut从与门输出。 同时，不再输出启用信号Grant的器件，并且包括具有反相器的Muller C元件的环路，OR门和AND门被取消。 结果，令牌（反馈信号S）被传送到下一个转换信令电路。

公开(公告)号：US06462981B2

公开(公告)日：2002-10-08

申请号：US09884669

申请日：2001-06-19

Applicant: Hideaki Numata ,  Koichi Takeda

Inventor： Hideaki Numata ,  Koichi Takeda

IPC: G11C1100

CPC classification number: G11C11/16 ,  G11C11/15 ,  Y10S977/943

Abstract: A matrix array of memory cells are located on intersections of word lines and sense lines. Each memory cell includes a magnetoresistance element and a switching element which establishes a resistive connection between a corresponding sense line and the magnetoresistance element when a corresponding word line is addressed. A number of sense circuits are respectively correspond to the sense lines. Each sense circuit includes a capacitive element connected to the corresponding sense line and a switching element for applying a voltage to the capacitive element and removing the voltage when the corresponding sense line is addressed, thereby discharging energy from the capacitive element through the resistive connection to the magnetoresistance element. The voltage developed across the capacitive element of each sense circuit is used to produce a binary output signal representative of information stored in an address memory cell.

Abstract translation: 存储器单元的矩阵阵列位于字线和感测线的交点上。 每个存储单元包括磁阻元件和开关元件，当对应的字线被寻址时，该开关元件在对应的感测线和磁阻元件之间建立电阻连接。 多个感测电路分别对应于感测线。 每个感测电路包括连接到对应感测线的电容元件和用于向电容元件施加电压并在对应的感测线被寻址时去除电压的开关元件，从而通过电阻连接将能量从电容元件释放到 磁阻元件 在每个感测电路的电容元件两端产生的电压用于产生表示存储在地址存储单元中的信息的二进制输出信号。

公开(公告)号：US06288968B1

公开(公告)日：2001-09-11

申请号：US09429481

申请日：1999-10-29

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C800

CPC classification number: G11C8/18 ,  G11C8/12

Abstract: The present invention provides a semiconductor integrated circuit having: a plurality of basic blocks, at least one of the basic blocks being selectively activated in accordance with at least two types of selective signals, and each of the plurality of basic blocks having at least a circuit block and at least a receiver circuit connected to the circuit block; and at least one of signal generator connected to the plurality of basic blocks for generating the at least two types of selective signals which individually include control signals having the same level in order to transmit the at least two types of selective signals to the receiver circuit in activated one of the basic blocks, wherein if the at least two types of selective signals which individually include the control signals are inputted into the receiver circuit with different timings, then the receiver circuit generates an output signal which remains to have the same level as the control signal included in a latest-inputted one of the at least two types of selective signals.

Abstract translation: 本发明提供了一种半导体集成电路，其具有：多个基本块，所述基本块中的至少一个根据至少两种类型的选择信号选择性地激活，并且所述多个基本块中的每一个具有至少一个电路 块和至少一个连接到电路块的接收器电路; 以及连接到所述多个基本块的信号发生器中的至少一个，用于产生所述至少两种类型的选择信号，所述选择信号分别包括具有相同电平的控制信号，以便将所述至少两种类型的选择信号发射到接收器电路 激活基本块中的一个，其中如果将具有控制信号的至少两种类型的选择信号以不同的定时输入到接收机电路中，则接收器电路产生一个输出信号，该输出信号保持与 所述控制信号包括在所述至少两种类型的选择信号中的最新输入的一个中。

公开(公告)号：US06226220B1

公开(公告)日：2001-05-01

申请号：US09664384

申请日：2000-09-18

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C800

CPC classification number: G11C11/419

Abstract: The present invention provides a semiconductor memory device comprising: at least one memory cell array further comprising: a plurality of word lines; plural pairs of bit lines; plural memory cells, each of the memory cells being connected to both one of the word line and one pair of the bit lines; a same number of column selecting circuits as the pairs of bit lines so that each of the column selecting circuits is connected to corresponding one pair of the bit lines; a write driver connected in parallel to the column selecting circuits; a sense amplifier connected in parallel to the column selecting circuits and the sense amplifier being activated for read operation and being inactivated for write operation; and a same number of read/write common column selecting lines as the pairs of bit lines so that each of the read/write common column selecting lines is connected to corresponding one of the column selecting circuits; a row decoder connected to the word lines for activating one of the word lines; and a column decoder connected to the read/write common column selecting lines for activating selected one of the read/write common column selecting lines for both read and write operations.

Abstract translation: 本发明提供了一种半导体存储器件，包括：至少一个存储单元阵列，还包括：多个字线; 多对位线; 多个存储单元，每个存储器单元连接到字线和一对位线中的一个; 与位线对相同数量的列选择电路，使得每个列选择电路连接到对应的一对位线; 与列选择电路并联连接的写入驱动器; 一个与列选择电路并联连接的读出放大器，读出放大器被激活用于读取操作，并且被激活以进行写操作; 以及与位线对相同数量的读/写公共列选择线，使得每个读/写公共列选择线连接到相应的列选择电路; 连接到用于激活字线之一的字线的行解码器; 以及连接到读/写公共列选择线的列解码器，用于激活用于读取和写入操作的读/写公共列选择线中的所选择的一个。

公开(公告)号：US5190832A

公开(公告)日：1993-03-02

申请号：US811066

申请日：1991-12-20

Applicant: Hiroyuki Ogawa ,  Tetsuo Ishitsuka ,  Kozo Denpo ,  Akihiro Miyasaka ,  Koichi Takeda ,  Satoshi Araki

Inventor： Hiroyuki Ogawa ,  Tetsuo Ishitsuka ,  Kozo Denpo ,  Akihiro Miyasaka ,  Koichi Takeda ,  Satoshi Araki

IPC: B32B15/01 ,  C22C19/07 ,  C22C30/00

CPC classification number: B32B15/01 ,  C22C19/07 ,  C22C30/00 ,  Y10S138/06 ,  Y10T428/12931

Abstract: An alloy exhibiting corrosion resistance in a combustion environment where V, Na, S and Cl are present comprises, in weight percent, not more than 0.05% C, 0.02-0.5% Si, 0.02-0.5% Mn, 15-35% Cr, 0.5-4% Mo, more than 40% but not more than 60% Co, 5-15% Fe, 0.5-5% W, 0.0003-0.005% Ca and the remainder of Ni at a content of not less than 4% and unavoidable impurities, provided that Cr (%)+0.5Ni (%)+3Mo (%).gtoreq.30 (%). A composite steel tube exhibiting corrosion resistance in a combustion environment where V, Na, S and Cl are present comprises an inner tube constituted of Cr-containing boiler tube and an outer tube constituted of the alloy.

公开(公告)号：US4393449A

公开(公告)日：1983-07-12

申请号：US156654

申请日：1980-06-05

Applicant: Koichi Takeda ,  Yoshiro Sasano

Inventor： Koichi Takeda ,  Yoshiro Sasano

IPC: G05B19/409 ,  G05B19/42

CPC classification number: G05B19/409 ,  G05B2219/35269 ,  G05B2219/35525 ,  G05B2219/36185 ,  G05B2219/37103 ,  G05B2219/37183 ,  G05B2219/50025 ,  G05B2219/50031 ,  Y02P90/265

Abstract: A numerically controlled machine tool is provided which comprises an operation control unit with an operating panel having key switches disposed thereon whereby data on the finish shape and finish dimensions of a workpiece and the machining conditions including spindle rpm and feed rate can be transferred into a control unit. On the basis of this input, the control unit automatically prepares a processing program which decides on the amounts and directions of movement of the tool rest longitudinally and transversely from a reference point which is inherent in the machine and controls the movement in accordance therewith so as to automatically machine the workpiece to the predetermined shape and dimensions. A desired final processing shape may be designated by using function keys on the operating panel bearing words in everyday or conversational language, whereupon the control unit automatically decides what is the data necessary for the particular machining that should be put in and then it turns on guide lamps corresponding to the decided data successively in the order in which the data should be put in, so as to guide the operator. Thus, it is only necessary for the operator to put in specific numerical values by means of ten-keys under the guidance.

Abstract translation: 提供了一种数控机床，其包括具有操作面板的操作控制单元，操作面板具有设置在其上的键开关，其中精加工形状和工件的精加工尺寸数据以及包括主轴转速和进给速率的加工条件可以被转移到控制 单元。 在该输入的基础上，控制单元自动地准备一个处理程序，该处理程序从机器固有的参考点纵向和横向地决定刀架的移动量和方向，并根据该参考点控制运动，以便 自动将工件加工成预定的形状和尺寸。 期望的最终处理形状可以通过使用日常或会话语言的操作面板上的功能键来指定，于是控制单元自动决定应该放入的特定加工所需的数据，然后打开导向 相应于所决定的数据的灯以连续的数据顺序放置，以便指导操作者。 因此，操作员只需要在指导下通过十键放入具体的数值。

公开(公告)号：US08559250B2

公开(公告)日：2013-10-15

申请号：US13471360

申请日：2012-05-14

Applicant: Hidetoshi Ikeda ,  Koichi Takeda

Inventor： Hidetoshi Ikeda ,  Koichi Takeda

IPC: G11C7/08

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1048 ,  G11C11/419

Abstract: Provided is a semiconductor memory device including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each row of the memory cells, a plurality of bit line pairs arranged corresponding to each column of the memory cells, a column selector that selects any of the plurality of bit line pairs based on a column selection signal and connects the selected bit line pair to a data line pair, a precharge circuit that precharges the data line pair, a sense amplifier that amplifies a potential difference of the data line pair, and a control circuit that controls current for driving the sense amplifier based on potentials of the data line pair after a lapse of a specified period from start of amplification of the potential difference of the precharged data line pair by the sense amplifier.

Abstract translation: 提供了一种半导体存储器件，其包括以矩阵形式布置的多个存储器单元，对应于存储器单元的每一行布置的多个字线，对应于存储器单元的每列布置的多个位线对，列 选择器，其基于列选择信号选择多个位线对中的任何一个，并将所选择的位线对连接到数据线对，预充电数据线对的预充电电路，放大电位差的读出放大器 数据线对以及控制电路，其控制电流，用于在由读出放大器从预充电数据线对的电位差的放大开始经过指定时段之后基于数据线对的电位驱动读出放大器。