Semiconductor device having plural conductive layers disposed within dielectric layer
    31.
    发明授权
    Semiconductor device having plural conductive layers disposed within dielectric layer 有权
    具有设置在电介质层内的多个导电层的半导体器件

    公开(公告)号:US08519541B2

    公开(公告)日:2013-08-27

    申请号:US12228764

    申请日:2008-08-14

    IPC分类号: H01L23/532

    摘要: A method for manufacturing a semiconductor device is disclosed. A semiconductor substrate such as bare silicon is provided, and a dielectric layer is formed over the semiconductor substrate. An opening is provided within the dielectric layer by removing a portion of the dielectric layer. A conformal first conductive layer is formed over the dielectric layer and the opening. A conformal second conductive layer is formed over the first conductive layer. A conformal barrier layer is formed over the second conductive layer.

    摘要翻译: 公开了一种制造半导体器件的方法。 提供诸如裸硅的半导体衬底,并且在半导体衬底上形成电介质层。 通过去除介电层的一部分,在电介质层内提供开口。 在电介质层和开口上形成共形的第一导电层。 在第一导电层上形成共形的第二导电层。 在第二导电层上形成共形势垒层。

    Method of reducing wordline shorting
    32.
    发明授权
    Method of reducing wordline shorting 有权
    减少字线短路的方法

    公开(公告)号:US08445346B2

    公开(公告)日:2013-05-21

    申请号:US12611614

    申请日:2009-11-03

    IPC分类号: H01L21/8247

    摘要: A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface.

    摘要翻译: 一种制造存储器件的方法包括提供具有绝缘层的衬底,在绝缘层上形成第一,第二和第三导电层,在第三导电层上形成掩模,蚀刻通过第三导电层和第一部分厚度 使用所述掩模提供所述第三导电层的蚀刻侧壁部分和所述第二多晶硅层的蚀刻的上表面,以及沿着蚀刻的侧壁部分和所蚀刻的上表面形成衬垫层。

    METHODOLOGY FOR WORDLINE SHORT REDUCTION
    33.
    发明申请
    METHODOLOGY FOR WORDLINE SHORT REDUCTION 有权
    短线减少的方法

    公开(公告)号:US20120122296A1

    公开(公告)日:2012-05-17

    申请号:US12947309

    申请日:2010-11-16

    IPC分类号: H01L21/28

    CPC分类号: H01L27/11568 H01L21/76224

    摘要: The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) providing a plurality of SASTIs with a plurality of first POLY cells deposited thereon; and (b) depositing a first fill-in material having a relatively high etching rate oxide-like material in the plurality of SASTIs and on each side wall of the plurality of first POLY cells.

    摘要翻译: 在本发明中提供了形成字线的方法。 所提出的方法包括以下步骤:(a)向多个SASTI提供多个沉积在其上的第一POLY单元; 和(b)在所述多个SASTI中和所述多个第一POLY电池的每个侧壁上沉积具有相对高蚀刻速率氧化物样材料的第一填充材料。

    PAD AND METHOD FOR CHEMICAL MECHANICAL POLISHING
    35.
    发明申请
    PAD AND METHOD FOR CHEMICAL MECHANICAL POLISHING 审中-公开
    PAD和化学机械抛光方法

    公开(公告)号:US20120040532A1

    公开(公告)日:2012-02-16

    申请号:US13281162

    申请日:2011-10-25

    IPC分类号: H01L21/306

    CPC分类号: B24B37/24 B24D3/346

    摘要: A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.

    摘要翻译: 提供了半导体器件的两个相邻结构的化学机械抛光方法。 一种用于机械抛光的方法,包括:(a)提供半导体器件,其包括在其表面形成的凹部,形成在所述表面上的第一层,以及填充有所述凹部并形成在所述第一层上的第二层; 和(b)用垫和基本上无抑制剂的浆料基本上抛光第一层和第二层,其中该垫包括第二层的腐蚀抑制剂。

    Methods and systems for mobile device messaging
    36.
    发明授权
    Methods and systems for mobile device messaging 有权
    移动设备消息传递的方法和系统

    公开(公告)号:US08112103B2

    公开(公告)日:2012-02-07

    申请号:US10759642

    申请日:2004-01-16

    IPC分类号: H04W4/00

    摘要: Embodiments of the present invention relate to methods, systems, and computer-readable media for mobile device messaging. Mobile device messaging comprises collecting from an originating system information including content data to be sent to the mobile device. One or more short messages are generating for encapsulating the content data. The one or more short messages are formatted to be readable by a web service and the content data is formatted to be readable by the mobile device. The one or more short messages are sent to the web service for delivery to the mobile device.

    摘要翻译: 本发明的实施例涉及用于移动设备消息收发的方法,系统和计算机可读介质。 移动设备消息收发包括从始发系统收集包括要发送到移动设备的内容数据的信息。 生成用于封装内容数据的一个或多个短消息。 一个或多个短消息被格式化为可由web服务读取,并且内容数据被格式化为可由移动设备读取。 一个或多个短消息被发送到web服务以传送到移动设备。

    CONTACT BARRIER LAYER DEPOSITION PROCESS
    37.
    发明申请
    CONTACT BARRIER LAYER DEPOSITION PROCESS 审中-公开
    联系障碍层沉积过程

    公开(公告)号:US20110056432A1

    公开(公告)日:2011-03-10

    申请号:US12945666

    申请日:2010-11-12

    IPC分类号: H01L21/4763

    摘要: A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma (IMP) physical vapor deposition process. The IMP process includes: generating gaseous ions, accelerating the gaseous ions towards a titanium target, sputtering the titanium atoms from the titanium target with the gaseous ions, ionizing the titanium atoms using a plasma, and depositing the ionized titanium atoms onto the substrate to form the layer of Ti. A first layer of titanium nitride (TiN) is deposited onto the layer of Ti using a metal organic chemical vapor deposition (MOCVD) process. A second layer of TiN is deposited onto the first layer of TiN using a thermal chemical vapor deposition process. The newly completed barrier layer is annealed in the presence of nitrogen at a temperature of between about 500° C. to about 750° C.

    摘要翻译: 公开了一种在衬底上沉积阻挡层的方法。 使用电离金属等离子体(IMP)物理气相沉积工艺将一层钛(Ti)沉积到衬底上。 IMP过程包括:产生气体离子,将气态离子加速到钛靶,用钛离子溅射钛原子与气态离子,使用等离子体离子化钛原子,并将离子化的钛原子沉积到基底上形成 Ti层。 使用金属有机化学气相沉积(MOCVD)工艺将第一层氮化钛(TiN)沉积到Ti层上。 使用热化学气相沉积工艺将第二层TiN沉积到第一TiN层上。 将新完成的阻挡层在氮气存在下在约500℃至约750℃的温度下进行退火。

    Multifunctional SPA Device
    38.
    发明申请
    Multifunctional SPA Device 审中-公开
    多功能SPA设备

    公开(公告)号:US20110047691A1

    公开(公告)日:2011-03-03

    申请号:US12551629

    申请日:2009-09-01

    IPC分类号: A61H33/04

    CPC分类号: A61H33/02 A61H33/60

    摘要: A multifunctional SPA device comprises: a pump, a vent pipe connected to an inlet end of the pump, and a jet connected to an outlet end of the pump, so that air will be sucked by the vent pipe and mixed with water in the pump when the pump sucks water via an intake pipe, allowing the jet to pump out water column containing rich micro bubbles.

    摘要翻译: 多功能SPA装置包括:泵,连接到泵的入口端的通气管和连接到泵的出口端的射流,使得空气将被排气管吸入并与泵中的水混合 当泵通过进气管吸入水时,允许喷射泵抽出含有富微小气泡的水柱。

    Method for forming self-aligned contacts and local interconnects simultaneously
    39.
    发明授权
    Method for forming self-aligned contacts and local interconnects simultaneously 有权
    同时形成自对准触点和局部互连的方法

    公开(公告)号:US07888804B2

    公开(公告)日:2011-02-15

    申请号:US12113855

    申请日:2008-05-01

    IPC分类号: H01L23/48

    摘要: The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts and the local interconnects to be widened, which makes the patterning of self-aligned contacts and local interconnects easier. The widened minimal distance requirement also allows further memory cell shrinkage. The improved structures of self-aligned contacts and local interconnects also have excellent isolation characteristic.

    摘要翻译: 本发明一般涉及半导体,更具体地涉及半导体存储器件结构和改进的制造方法。 改进的制造工艺允许自对准触点和局部互连同时处理。 该过程允许自对准触点和局部互连之间的最小距离要求加宽,这使得自对准触点和局部互连的图案化变得更容易。 扩大的最小距离要求也允许进一步的记忆体细胞收缩。 自对准触点和局部互连的改进结构也具有优异的隔离特性。

    Interconnection process
    40.
    发明授权
    Interconnection process 有权
    互连过程

    公开(公告)号:US07625819B2

    公开(公告)日:2009-12-01

    申请号:US11806541

    申请日:2007-06-01

    IPC分类号: H01L21/44 H01L21/4763

    摘要: An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole.

    摘要翻译: 提供互连过程。 该过程包括以下步骤。 首先,设置至少具有导电区域的半导体基板。 接下来,形成具有接触孔的电介质层以覆盖半导体基底,其中接触孔暴露部分导电区域。 然后,对覆盖有电介质层的半导体基板进行热处理。 最后,在电介质层上形成导电层,其中导电层通过接触孔与导电区电连接。