公开(公告)号：US20110075502A1

公开(公告)日：2011-03-31

申请号：US12648774

申请日：2009-12-29

Applicant: Kyong Ha LEE

Inventor： Kyong Ha LEE

IPC: G11C8/00

CPC classification number: G11C11/4087 ,  G11C2207/107

Abstract: The bank active signal generation circuit comprises a decoded signal generator and an active signal generator. The decoded signal generator generates decoded signals from a first bank access signal, a second bank access signal and a row address signal in response to when a prefetch signal at a first mode. The decoded signal generator also generates decoded signals from the first bank access signal, the second bank access signal, and a third bank access signal in response when the prefetch signal at a second mode. The active signal generator generates bank active signals in response to receiving the decoded signals, an active pulse and a precharge pulse.

Abstract translation: 存储体活动信号发生电路包括解码信号发生器和有源信号发生器。 解码信号发生器响应于何时处于第一模式的预取信号，从第一存储体存取信号，第二存​​储体存取信号和行地址信号产生解码信号。 当处于第二模式的预取信号时，解码信号发生器还产生来自第一存储体存取信号，第二存​​储体存取信号和第三存储体存取信号的解码信号。 响应于接收到解码信号，有效脉冲和预充电脉冲，有源信号发生器产生存储体有效信号。

公开(公告)号：US07800966B2

公开(公告)日：2010-09-21

申请号：US12001667

申请日：2007-12-12

Applicant: Kyong Ha Lee ,  Jong Won Lee

Inventor： Kyong Ha Lee ,  Jong Won Lee

IPC: G11C7/00

CPC classification number: G11C7/12

Abstract: A precharge control circuit includes a precharge control unit and a precharge unit. The precharge control unit controls and outputs a precharge signal in response to a read command signal, a write command signal, and a first signal. The precharge unit precharges local input/output lines in response to a signal output from the precharge control unit.

Abstract translation: 预充电控制电路包括预充电控制单元和预充电单元。 预充电控制单元响应于读命令信号，写命令信号和第一信号来控制和输出预充电信号。 预充电单元响应于从预充电控制单元输出的信号，对本地输入/输出线进行预充电。

公开(公告)号：US07633832B2

公开(公告)日：2009-12-15

申请号：US11826923

申请日：2007-07-19

Applicant: Kyong-Ha Lee

Inventor： Kyong-Ha Lee

IPC: G11C8/00

CPC classification number: H03K5/135 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  H03K17/223 ,  H03L1/00

Abstract: A circuit for outputting data of a semiconductor memory apparatus is provided. A circuit for outputting data of a semiconductor memory apparatus according to an embodiment of the present invention includes a data clock generating unit that generates a data clock, a delayed clock generating unit that receives the data clock and outputs a delayed clock according to a change in an external voltage level, and a clock synchronizing unit that outputs data synchronized with the delayed clock as output data.

Abstract translation: 提供一种用于输出半导体存储装置的数据的电路。 根据本发明实施例的用于输出半导体存储装置的数据的电路包括：数据时钟产生单元，用于产生数据时钟;延迟时钟产生单元，用于接收数据时钟并输出延迟时钟， 外部电压电平和时钟同步单元，其输出与延迟时钟同步的数据作为输出数据。

公开(公告)号：US20080151680A1

公开(公告)日：2008-06-26

申请号：US11826923

申请日：2007-07-19

Applicant: Kyong-Ha Lee

Inventor： Kyong-Ha Lee

IPC: G11C8/18

CPC classification number: H03K5/135 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  H03K17/223 ,  H03L1/00

Abstract: A circuit for outputting data of a semiconductor memory apparatus is provided. A circuit for outputting data of a semiconductor memory apparatus according to an embodiment of the present invention includes a data clock generating unit that generates a data clock, a delayed clock generating unit that receives the data clock and outputs a delayed clock according to a change in an external voltage level, and a clock synchronizing unit that outputs data synchronized with the delayed clock as output data.

Abstract translation: 提供一种用于输出半导体存储装置的数据的电路。 根据本发明实施例的用于输出半导体存储装置的数据的电路包括：数据时钟产生单元，用于产生数据时钟;延迟时钟产生单元，用于接收数据时钟并输出延迟时钟， 外部电压电平和时钟同步单元，其输出与延迟时钟同步的数据作为输出数据。

公开(公告)号：US08699276B2

公开(公告)日：2014-04-15

申请号：US13591306

申请日：2012-08-22

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222

Abstract: A semiconductor memory device including a first edge region for receiving a write command through a first pad portion to generate a column enable signal used in creation of a column selection signal; a second edge region including a data transmission control circuit capable of receiving an input data and a data strobe signal through a second pad portion and capable of receiving an address signal from the first pad portion to generate and output transmission data, the data transmission control circuit capable of outputting the column enable signal transmitted from the first edge region; and a core region including a column control portion that is capable of processing the transmission data in response to the column enable signal outputted from the second edge region to send the transmission data to bit lines electrically connected to memory cells.

Abstract translation: 一种半导体存储器件，包括：第一边缘区域，用于通过第一焊盘部分接收写入命令，以产生用于创建列选择信号的列使能信号; 第二边缘区域，包括能够通过第二焊盘部分接收输入数据和数据选通信号的数据传输控制电路，并且能够从第一焊盘部分接收地址信号以产生和输出传输数据，数据传输控制电路 能够输出从第一边缘区域发送的列使能信号; 以及核心区域，包括列控制部分，其能够响应于从第二边缘区域输出的列使能信号来处理传输数据，以将传输数据发送到与存储器单元电连接的位线。

公开(公告)号：US08233348B2

公开(公告)日：2012-07-31

申请号：US12648774

申请日：2009-12-29

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C8/00

CPC classification number: G11C11/4087 ,  G11C2207/107

Abstract: The bank active signal generation circuit comprises a decoded signal generator and an active signal generator. The decoded signal generator generates decoded signals from a first bank access signal, a second bank access signal and a row address signal in response to when a prefetch signal at a first mode. The decoded signal generator also generates decoded signals from the first bank access signal, the second bank access signal, and a third bank access signal in response when the prefetch signal at a second mode. The active signal generator generates bank active signals in response to receiving the decoded signals, an active pulse and a precharge pulse.

Abstract translation: 存储体活动信号发生电路包括解码信号发生器和有源信号发生器。 解码信号发生器响应于何时处于第一模式的预取信号，从第一存储体存取信号，第二存​​储体存取信号和行地址信号产生解码信号。 当处于第二模式的预取信号时，解码信号发生器还产生来自第一存储体存取信号，第二存​​储体存取信号和第三存储体存取信号的解码信号。 响应于接收到解码信号，有效脉冲和预充电脉冲，有源信号发生器产生存储体有效信号。

公开(公告)号：US20100246310A1

公开(公告)日：2010-09-30

申请号：US12459362

申请日：2009-06-30

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C8/06 ,  G11C7/10 ,  G11C8/00

CPC classification number: G11C8/12

Abstract: A semiconductor memory includes an address converting circuit which latches an address and a bank signal and generates a latch address for activating a data access path of a second bank group, and converts the latch address according to a level of the bank signal and generates a variable address for activating a data access path of a first bank group, a first column decoder which decodes the variable address and generates a first output enable signal for activating the data access path of the first bank group, and a second column decoder which decodes the latch address and generates a second output enable signal for activating the data access path of the second bank group.

Abstract translation: 半导体存储器包括地址转换电路，其锁存地址和存储体信号，并产生用于激活第二组组的数据存取路径的锁存地址，并根据存储体信号的电平转换锁存器地址，并产生变量 用于激活第一组组的数据访问路径的地址;解码可变地址并产生用于激活第一组组的数据访问路径的第一输出使能信号的第一列解码器，以及解码锁存器的第二列解码器 地址并产生用于激活第二组组的数据访问路径的第二输出使能信号。

公开(公告)号：US07486583B2

公开(公告)日：2009-02-03

申请号：US11497899

申请日：2006-08-01

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C2211/4065

Abstract: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a shift register configured to receive an oscillation signal that is periodically enabled after a self-refresh signal is enabled, to allow a self-refresh operation to be performed, and delay the received oscillation signal by a unit self-refresh period to output a delayed oscillation signal, a period measurement start signal generator configured to receive the self-refresh signal and the oscillation signal and generate a period measurement start signal for setting a time that the oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period, and a refresh period output unit configured to receive the period measurement start signal and the delayed oscillation signal from the shift register and generate a refresh period output signal that is enabled for a period from a time that the period measurement start signal is enabled to a time that the delayed oscillation signal is enabled for the first time.

Abstract translation: 公开了一种半导体器件的自刷新周期测量电路，其中包括：移位寄存器，被配置为在自刷新信号被使能之后接收周期性地使能的振荡信号，以允许执行自刷新操作; 并且将所接收的振荡信号延迟单位自刷新周期以输出延迟的振荡信号;周期测量开始信号发生器，被配置为接收所述自刷新信号和所述振荡信号，并产生周期测量开始信号， 第一次使振荡信号作为测量自刷新周期的开始时间，以及刷新周期输出单元，被配置为从移位寄存器接收周期测量开始信号和延迟的振荡信号，并产生刷新周期 输出信号在从周期测量开始信号有效的时间到该时间的一段时间内被使能 e延迟振荡信号第一次使能。

公开(公告)号：US20090003106A1

公开(公告)日：2009-01-01

申请号：US12001667

申请日：2007-12-12

Applicant: Kyong Ha Lee ,  Jong Won Lee

Inventor： Kyong Ha Lee ,  Jong Won Lee

IPC: G11C7/00

CPC classification number: G11C7/12

Abstract: A precharge control circuit includes a precharge control unit and a precharge unit. The precharge control unit controls and outputs a precharge signal in response to a read command signal, a write command signal, and a first signal. The precharge unit precharges local input/output lines in response to a signal output from the precharge control unit.

Abstract translation: 预充电控制电路包括预充电控制单元和预充电单元。 预充电控制单元响应于读命令信号，写命令信号和第一信号来控制和输出预充电信号。 预充电单元响应于从预充电控制单元输出的信号，对本地输入/输出线进行预充电。

公开(公告)号：US20070237017A1

公开(公告)日：2007-10-11

申请号：US11638363

申请日：2006-12-14

Applicant: Kyong-Ha Lee

Inventor： Kyong-Ha Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C2211/4061

Abstract: An apparatus for detecting a refresh period of a semiconductor memory includes a signal generating unit that generates a plurality of signal pairs, each of which includes one among a plurality of first reference signals that are respectively generated with the same timing as first to (N−1)-th pulses of a refresh period signal of order N, and one among a plurality of second reference signals that correspond to the plurality of first reference signals and are respectively generated with the same timing as second to N-th pulses of the refresh period signal. A refresh period detecting unit detects the period of the refresh period signal using one among the plurality of signal pairs.

Abstract translation: 一种用于检测半导体存储器的刷新周期的装置，包括产生多个信号对的信号产生单元，每个信号对都包括分别以与第一至第（N）个相同的时序生成的多个第一参考信号之一， 1次刷新周期信号的序列N的脉冲，以及与多个第一参考信号相对应的多个第二参考信号中的一个脉冲，并分别以与刷新的第二至第N个脉冲相同的定时生成 周期信号。 刷新周期检测单元使用多个信号对中的一个来检测刷新周期信号的周期。