公开(公告)号：US08520466B2

公开(公告)日：2013-08-27

申请号：US13560370

申请日：2012-07-27

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C8/00

CPC classification number: G11C7/1018 ,  G11C7/1039 ,  G11C11/4076

Abstract: The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command.

Abstract translation: 内部命令生成电路包括脉冲串脉冲发生单元和脉冲移位单元。 突发脉冲发生单元被配置为接收用于读取或写入操作的命令，并且生成第一突发脉冲。 脉冲移位单元被配置为移位第一突发脉冲并产生内部命令。

公开(公告)号：US08050137B2

公开(公告)日：2011-11-01

申请号：US12493755

申请日：2009-06-29

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C8/18

CPC classification number: G11C7/222 ,  G11C7/1027 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C8/04 ,  G11C8/10

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract translation: 半导体集成电路包括命令解码器，移位寄存器单元和命令地址锁存单元。 命令解码器响应于定义写入和读取模式的外部命令，并且被配置为使用上升或下降时钟根据外部命令提供写入命令或读取命令。 移位寄存器单元被配置为响应写入命令将外部地址和写入命令移位写入延迟。 列地址锁存单元被配置为在读取模式下锁存并提供外部地址作为列地址，并锁存从移位寄存器单元提供的写入地址，并将写入地址作为列地址提供给 写模式。

公开(公告)号：US20090180344A1

公开(公告)日：2009-07-16

申请号：US12319879

申请日：2009-01-13

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C2211/4065

Abstract: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a delay means for delaying the received oscillation signal by a unit self-refresh period to output a first delayed oscillation signal, and delaying the received oscillation signal to output a third delayed oscillation signal, a first period measurement start signal generator for generating a first period measurement start signal for setting a time that the oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period, and a first refresh period output unit for generating a first refresh period output signal that is enabled for a period from a time that the first period measurement start signal is enabled to a time that the first delayed oscillation signal is enabled for the first time.

Abstract translation: 本发明公开了一种半导体器件的自刷新周期测量电路，其中包括延迟装置，用于将接收的振荡信号延迟单位自刷新周期以输出第一延迟振荡信号，并延迟所接收的振荡信号以输出 第一延迟振荡信号，第一周期测量开始信号发生器，用于产生用于设置第一次使能振荡信号的时间的第一周期测量开始信号作为测量自刷新周期的开始时间，以及第一延迟振荡信号 刷新周期输出单元，用于产生第一刷新周期输出信号，该第一刷新周期输出信号在从第一周期测量开始信号使能到第一次启用第一延迟振荡信号的时间之间的期间被使能。

公开(公告)号：US07551504B2

公开(公告)日：2009-06-23

申请号：US11638363

申请日：2006-12-14

Applicant: Kyong-Ha Lee

Inventor： Kyong-Ha Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C2211/4061

Abstract: An apparatus for detecting a refresh period of a semiconductor memory includes a signal generating unit that generates a plurality of signal pairs, each of which includes one among a plurality of first reference signals that are respectively generated with the same timing as first to (N−1)-th pulses of a refresh period signal of order N, and one among a plurality of second reference signals that correspond to the plurality of first reference signals and are respectively generated with the same timing as second to N-th pulses of the refresh period signal. A refresh period detecting unit detects the period of the refresh period signal using one among the plurality of signal pairs.

Abstract translation: 一种用于检测半导体存储器的刷新周期的装置，包括产生多个信号对的信号产生单元，每个信号对都包括分别以与第一至第（N）个相同的时序生成的多个第一参考信号之一， 1次刷新周期信号的序列N的脉冲，以及与多个第一参考信号相对应的多个第二参考信号中的一个脉冲，并分别以与刷新的第二至第N个脉冲相同的定时生成 周期信号。 刷新周期检测单元使用多个信号对中的一个来检测刷新周期信号的周期。

公开(公告)号：US07548478B2

公开(公告)日：2009-06-16

申请号：US11976356

申请日：2007-10-24

Applicant: Kyong-Ha Lee

Inventor： Kyong-Ha Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/401 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50016 ,  G11C2211/4061

Abstract: The present invention provides a self-refresh period adaptable for testing cells that are weak against hot temperature stress. An apparatus for controlling a self-refresh operation in a semiconductor memory device includes a first period selector for generating one of a period-fixed pulse signal having a constant period and a period-variable pulse signal having a variable period based on a temperature of the semiconductor memory device in a test mode; and a self-refresh block for performing the self-refresh operation in response to an output of the first period selector.

Abstract translation: 本发明提供适用于测试对热温度应力弱的细胞的自刷新周期。 一种用于控制半导体存储器件中的自刷新操作的装置包括：第一周期选择器，用于产生具有恒定周期的周期固定脉冲信号和基于温度的可变周期的周期可变脉冲信号 半导体存储器件处于测试模式; 以及自刷新块，用于响应于第一周期选择器的输出执行自刷新操作。

公开(公告)号：US20060221745A1

公开(公告)日：2006-10-05

申请号：US11320650

申请日：2005-12-30

Applicant: Kyong-Ha Lee

Inventor： Kyong-Ha Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/401 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50016 ,  G11C2211/4061

Abstract: The present invention provides a self-refresh period adaptable for testing cells that are weak against hot temperature stress. An apparatus for controlling a self-refresh operation in a semiconductor memory device includes a first period selector for generating one of a period-fixed pulse signal having a constant period and a period-variable pulse signal having a variable period based on a temperature of the semiconductor memory device in a test mode; and a self-refresh block for performing the self-refresh operation in response to an output of the first period selector.

公开(公告)号：US08953410B2

公开(公告)日：2015-02-10

申请号：US13241847

申请日：2011-09-23

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10 ,  G11C8/04 ,  G11C8/10

CPC classification number: G11C7/222 ,  G11C7/1027 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C8/04 ,  G11C8/10

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract translation: 半导体集成电路包括命令解码器，移位寄存器单元和命令地址锁存单元。 命令解码器响应于定义写入和读取模式的外部命令，并且被配置为使用上升或下降时钟根据外部命令提供写入命令或读取命令。 移位寄存器单元被配置为响应写入命令将外部地址和写入命令移位写入延迟。 列地址锁存单元被配置为在读取模式下锁存并提供外部地址作为列地址，并锁存从移位寄存器单元提供的写入地址，并将写入地址作为列地址提供给 写模式。

公开(公告)号：US20130223160A1

公开(公告)日：2013-08-29

申请号：US13591306

申请日：2012-08-22

Applicant: Kyong Ha LEE

Inventor： Kyong Ha LEE

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1084 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222

Abstract: A semiconductor memory device including a first edge region for receiving a write command through a first pad portion to generate a column enable signal used in creation of a column selection signal; a second edge region including a data transmission control circuit capable of receiving an input data and a data strobe signal through a second pad portion and capable of receiving an address signal from the first pad portion to generate and output transmission data, the data transmission control circuit capable of outputting the column enable signal transmitted from the first edge region; and a core region including a column control portion that is capable of processing the transmission data in response to the column enable signal outputted from the second edge region to send the transmission data to bit lines electrically connected to memory cells.

Abstract translation: 一种半导体存储器件，包括：第一边缘区域，用于通过第一焊盘部分接收写入命令，以产生用于创建列选择信号的列使能信号; 第二边缘区域，包括能够通过第二焊盘部分接收输入数据和数据选通信号的数据传输控制电路，并且能够从第一焊盘部分接收地址信号以产生和输出传输数据，数据传输控制电路 能够输出从第一边缘区域发送的列使能信号; 以及核心区域，包括列控制部分，其能够响应于从第二边缘区域输出的列使能信号来处理传输数据，以将传输数据发送到与存储器单元电连接的位线。

公开(公告)号：US20120008452A1

公开(公告)日：2012-01-12

申请号：US13241847

申请日：2011-09-23

Applicant: Kyong Ha LEE

Inventor： Kyong Ha LEE

IPC: G11C8/18

CPC classification number: G11C7/222 ,  G11C7/1027 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C8/04 ,  G11C8/10

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract translation: 半导体集成电路包括命令解码器，移位寄存器单元和命令地址锁存单元。 命令解码器响应于定义写入和读取模式的外部命令，并且被配置为使用上升或下降时钟根据外部命令提供写入命令或读取命令。 移位寄存器单元被配置为响应写入命令将外部地址和写入命令移位写入延迟。 列地址锁存单元被配置为在读取模式下锁存并提供外部地址作为列地址，并锁存从移位寄存器单元提供的写入地址，并将写入地址作为列地址提供给 写模式。

公开(公告)号：US07986574B2

公开(公告)日：2011-07-26

申请号：US12459084

申请日：2009-06-26

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C7/00

CPC classification number: G11C11/4076 ,  G11C7/08 ,  G11C7/1072 ,  G11C8/18

Abstract: A data input circuit comprises a sensing control unit which delays an internal write command by a predetermined period and generates a sense amplifier enable signal in response to a first clock signal, and a data sensing unit which senses align data and transfers the sensed data to a global line in response to the sense amplifier enable signal, wherein the sense amplifier enable signal is enabled at a time point when the align data is inputted in the data sensing unit.

Abstract translation: 数据输入电路包括：感测控制单元，其将内部写入命令延迟预定周期，并响应于第一时钟信号产生读出放大器使能信号;以及数据感测单元，其感测对准数据并将感测数据传送到 全局线响应于读出放大器使能信号，其中读出放大器使能信号在校准数据被输入数据检测单元的时间点被使能。