公开(公告)号：US4825396A

公开(公告)日：1989-04-25

申请号：US14258

申请日：1987-02-12

申请人： Lajos Gazsi

发明人： Lajos Gazsi

IPC分类号： H03H17/00 ,  H03H17/02 ,  G06F15/31

CPC分类号： H03H17/0201

摘要： A digital circuit for sampling rate variation and signal filtering includes an input, an output, a lattice wave digital filter having a plurality of filter branches connected to the input, the filter branches each having at least two series-connected filter subgroups with basic filter elements each formed of one two port adaptor made up of adders and multipliers and one time-lag device, a device disposed between the at least two filter subgroups for varying the sampling rate and for generating a phase change in a digital system, and an adder connected between filter branches and the output. A method for constructing the circuit is also provided.

摘要翻译： 用于采样率变化和信号滤波的数字电路包括输入，输出，具有连接到输入的多个滤波器分支的格子波数字滤波器，每个滤波器分支具有至少两个具有基本滤波器元件的串联滤波器子组 每个由一个由加法器和乘法器组成的两个端口适配器和一个时间延迟器件形成，一个设置在该至少两个滤波器子组之间用于改变采样率并用于在数字系统中产生相位变化的装置，以及一个加法器 在过滤器分支和输出之间。 还提供了一种用于构建电路的方法。

公开(公告)号：US20150042310A1

公开(公告)日：2015-02-12

申请号：US13961990

申请日：2013-08-08

申请人： Lajos Gazsi ,  Stefan Meier ,  Matthias Schoebinger

发明人： Lajos Gazsi ,  Stefan Meier ,  Matthias Schoebinger

IPC分类号： G01R29/00

CPC分类号： G01R13/0272 ,  G01R29/00 ,  G04D7/003

摘要： A method for determining a sampling time of a signal, the method including: determining a candidate sampling time of a signal for input to a sampling circuit; determining a resultant sampling time at which the sampling circuit samples the signal when input with the candidate sampling time; and determining a sampling time of the signal based on a noise shaping of a difference between the resultant sampling time and the candidate sampling time.

摘要翻译： 一种用于确定信号的采样时间的方法，所述方法包括：确定用于输入到采样电路的信号的候选采样时间; 确定采样电路在用候选采样时间输入时采样信号的结果采样时间; 以及基于所得到的采样时间和候选采样时间之间的差的噪声整形来确定所述信号的采样时间。

公开(公告)号：US08018366B2

公开(公告)日：2011-09-13

申请号：US12615994

申请日：2009-11-10

申请人： Stephan Henzler ,  Matthias Schobinger ,  Lajos Gazsi

发明人： Stephan Henzler ,  Matthias Schobinger ,  Lajos Gazsi

IPC分类号： H03M1/12

CPC分类号： H03M1/125 ,  H03M1/504

摘要： Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).

摘要翻译： 公开了电路和系统的示例性实施方式，以及用于信号处理的方法，包括通过无源脉冲调制模数转换器（PMADC）实现的振幅和频带限制信号的采样和量化。

公开(公告)号：US07079538B2

公开(公告)日：2006-07-18

申请号：US09803384

申请日：2001-03-09

申请人： Lajos Gazsi ,  Xiaoning Nie

发明人： Lajos Gazsi ,  Xiaoning Nie

IPC分类号： H04L12/28 ,  H04J3/24

CPC分类号： H04L45/00 ,  H04L49/102

摘要： High-speed router for transmitting data packets, containing header data and useful data, between data networks, the router including a plurality of data processing processors for parallel data processing of the header data, a demultiplexer for separating the data packets into header data and useful data, and a distribution processor for distributing the separated header data among the data processing processors. The distribution processor distributes the header data at least in part on the basis of a priority specified by the header data and the workload of the data processing processors.

摘要翻译： 高速路由器，用于在数据网络之间传输包含标题数据和有用数据的数据包，路由器包括多个用于头文件数据并行数据处理的数据处理处理器，用于将数据包分离成标题数据和有用的解复用器 数据和用于在数据处理器之间分配分离的报头数据的分发处理器。 分发处理器至少部分地基于由标题数据指定的优先级和数据处理处理器的工作量来分发报头数据。

公开(公告)号：US06870879B2

公开(公告)日：2005-03-22

申请号：US09797244

申请日：2001-03-01

申请人： Lajos Gazsi ,  Reinhard Stolle

发明人： Lajos Gazsi ,  Reinhard Stolle

IPC分类号： H03H17/02 ,  H03H17/04 ,  H03H17/06 ,  H04L7/02 ,  H03K5/159 ,  G06F17/17 ,  H03M7/00 ,  H04L23/00

CPC分类号： H03H17/0416 ,  H03H17/0286 ,  H03H17/0288

摘要： Interpolation filter circuit for a digital communication device for the filtering and clock-rate conversion of a digital input signal received from a data source with a symbol-clock data rate, having (a) an FIR filter (4), which filters the digital input signal received with the symbol-clock data rate in such a way that, in the passband frequency range of the interpolation filter circuit (1), the power spectral density characteristic of the filtered digital output signal emitted by the interpolation filter circuit essentially coincides with a prescribed desired characteristic of the power spectral density PSDdes; (b) a resampling filter (6) connected downstream of the FIR filter (4) for increasing the clock data rate of the digital input signal filtered by the FIR filter (4); and having (c) an IIR filter (8), which is connected downstream of the resampling filter and filters the resampled digital signal emitted by the resampling filter (6) in such a way that, in the cutoff frequency range of the interpolation filter circuit (1), the power spectral density characteristic of the filtered digital output signal emitted by the interpolation filter circuit essentially coincides with the prescribed desired characteristic of the power spectral density PSDdes.

摘要翻译： 用于数字通信设备的插值滤波器电路，用于对具有符号时钟数据速率的数据源接收的数字输入信号进行滤波和时钟速率转换，其具有（a）FIR滤波器（4），其对数字输入进行滤波 以符号时钟数据速率接收的信号，使得在内插滤波器电路（1）的通带频率范围内，由内插滤波器电路发射的经滤波的数字输出信号的功率谱密度特性基本上与 功率谱密度PSDdes的规定期望特性;（b）连接在FIR滤波器（4）下游的重采样滤波器（6），用于增加由FIR滤波器（4）滤波的数字输入信号的时钟数据速率;以及 （c）IIR滤波器（8），其连接在重采样滤波器的下游并且滤波由重采样滤波器（6）发射的重采样的数字信号，使得在截止频率范围 内插滤波器电路（1）的滤波数字输出信号的功率谱密度特性基本上与功率谱密度PSDdes的规定期望特性一致。

公开(公告)号：US06829629B1

公开(公告)日：2004-12-07

申请号：US10019366

申请日：2002-06-12

申请人： Thomas Magesacher ,  Lajos Gazsi ,  Peter Caldera

发明人： Thomas Magesacher ,  Lajos Gazsi ,  Peter Caldera

IPC分类号： G06F1717

CPC分类号： H03H17/0671 ,  H03H17/0664

摘要： A comb filter arrangement has an integrator that outputs an input value to a signal path. The signal path includes a delay stage for adjusting the input value using a delay factor, a decimator that converts the input value into a decimated output value using a non-integral factor, a differentiator that generates an intermediate output value from the input value, and an interpolation arrangement that receives the intermediate output value and generates a decimated sequence of the output value.

摘要翻译： 梳状滤波器装置具有向信号路径输出输入值的积分器。 信号路径包括用于使用延迟因子调整输入值的延迟级，使用非积分因子将输入值转换为抽取的输出值的抽取器，从输入值生成中间输出值的微分器，以及 插值装置，其接收中间输出值并生成输出值的抽取序列。

公开(公告)号：US5805639A

公开(公告)日：1998-09-08

申请号：US535714

申请日：1995-09-28

申请人： Reiner Tonch ,  Lajos Gazsi ,  Ferenc Leeb

发明人： Reiner Tonch ,  Lajos Gazsi ,  Ferenc Leeb

IPC分类号： H03H21/00 ,  H04B3/06 ,  H04L25/06 ,  H03H7/30 ,  H03H7/40

CPC分类号： H03H21/0012 ,  H04L25/061 ,  H04L25/064

摘要： An adaptive network includes a summation node for receiving an input signal and delivering an output signal. A decision unit receives the output signal of the summation node as an input signal and has an output for delivering an output signal being a differential signal between the input and output signals of the decision unit. An adaptive feedback branch receives the output signal of the decision unit and has status variables, coefficients and an output. A changeover switch unit couples the output of the feedback branch to the summation node. A monitoring unit monitors an error magnitude of the output signal of the decision unit. The monitoring unit triggers the changeover switch unit in the next clock cycle if a first signal value having an amplitude exceeding a certain threshold value appears, for causing the summation node to be acted upon by a digital zero signal, for setting the status variables of the feedback branch to zero and for freezing the coefficients of the feedback branch.

摘要翻译： 自适应网络包括用于接收输入信号并传送输出信号的求和节点。 决定单元接收求和节点的输出信号作为输入信号，并且具有用于在作为判定单元的输入和输出信号之间传送作为差分信号的输出信号的输出。 自适应反馈分支接收决策单元的输出信号，并具有状态变量，系数和输出。 转换开关单元将反馈分支的输出耦合到求和节点。 监视单元监视决策单元的输出信号的误差大小。 如果出现振幅超过特定阈值的第一信号值，则监视单元在下一个时钟周期触发转换开关单元，以使求和节点被数字零信号作用，以便设置状态变量 反馈分支为零并冻结反馈分支的系数。

公开(公告)号：US5233548A

公开(公告)日：1993-08-03

申请号：US888473

申请日：1992-05-22

申请人： Lajos Gazsi ,  Dieter Bruckman

发明人： Lajos Gazsi ,  Dieter Bruckman

IPC分类号： H03H21/00

CPC分类号： H03H21/0012

摘要： A method and network configuration attain a continuous variation in the transfer function of an adaptive recursive network having multi-port subnetworks associated with parameters of the network, for processing discrete-time signals upon continuous variations in the parameters. The multi-port subnetworks are represented by elementary subnetworks being isolated with respect to the parameters. Each elementary subnetwork has parameters which can assume values in a given total value range being represented by a differently structured elementary subrange network being associated with adjacent value ranges of the respective parameter and having a transfer function varying continuously upon continuous variations in the parameter. A switchable inverter and elementary subnetworks having parameters which can only assume values in a range of the given total value range, are optionally represented by a combined subnetwork. The elementary subnetworks include first and second two-port adaptors each having first and second inputs and first and second outputs. A first adder is connected to the first and second inputs. A second adder is connected to the first input and the second output. A third adder is connected to the second input and the first output. A multiplier is connected between the output side of the first adder and the input sides of the second and third adders. The input side of the first adder of the first two-port adaptor is inverted with respect to the first input, and the input side of the third adder of the second two-port adaptor is inverted with respect to the multiplier.

摘要翻译： 一种方法和网络配置实现了具有与网络参数相关联的多端口子网络的自适应递归网络的传递函数的连续变化，用于在参数的连续变化时处理离散时间信号。 多端口子网由相对于参数隔离的基本子网来表示。 每个基本子网络具有参数，其可以假设给定总值范围内的值由不同结构化的基本子网络表示，其与相应参数的相邻值范围相关联，并且具有在参数的连续变化时连续变化的传递函数。 具有可以仅在给定总值范围的范围内的值的参数的可切换逆变器和基本子网络可选地由组合子网络表示。 基本子网包括第一和第二双端口适配器，每个具有第一和第二输入以及第一和第二输出。 第一加法器连接到第一和第二输入。 第二加法器连接到第一输入端和第二输出端。 第三加法器连接到第二输入端和第一输出端。 乘法器连接在第一加法器的输出侧和第二加法器和第三加法器的输入侧之间。 第一双端口适配器的第一加法器的输入侧相对于第一输入反相，并且第二双端口适配器的第三加法器的输入侧相对于乘法器反转。

公开(公告)号：US5204831A

公开(公告)日：1993-04-20

申请号：US805584

申请日：1991-12-11

申请人： Lajos Gazsi ,  Peter Caldera

发明人： Lajos Gazsi ,  Peter Caldera

IPC分类号： H03H17/02 ,  G06F7/48

CPC分类号： G06F7/48 ,  G06F7/49994

摘要： A circuit configuration for digital bit-serial signal processing includes n input shift registers each being written in parallel or serially with an input data word and then read out by shifting to the right. Sign repetition devices are each assigned to a respective one of the input shift registers for continuously generating and shifting an algebraic sign of the input data word onward in the shift to the right. A serial arithmetic unit is connected downstream of the input shift registers for serially outputting output data words. m output shift registers connected downstream of the serial arithmetic unit are written in serially with the output data words and read out in parallel and/or serially. A control unit is connected to the serial arithmetic unit. Once all of the output data words have been fully written in the respective output shift registers, the control unit ends a readout of the input shift registers and the writing in of the output shift registers, for bringing the arithmetic unit to a defined initial state, and for enabling the input shift registers for writing in new input data words.

摘要翻译： 用于数字位串行信号处理的电路配置包括n个输入移位寄存器，每个输入移位寄存器与输入数据字并行或串行写入，然后通过向右移位读出。 符号重复装置各自分配给输入移位寄存器中的相应一个，用于在向右移位中连续产生和移位输入数据字的代数符号。 串行运算单元连接在输入移位寄存器的下游，用于串行输出输出数据字。 连接在串行运算单元下游的m个输出移位寄存器与输出数据字串联写入并且/或串行读出。 控制单元连接到串行运算单元。 一旦所有输出数据字已被完全写入相应的输出移位寄存器中，则控制单元结束输入移位寄存器的读出和输出移位寄存器的写入，以使算术单元处于定义的初始状态， 并且用于使输入移位寄存器能够写入新的输入数据字。

公开(公告)号：US5172411A

公开(公告)日：1992-12-15

申请号：US676193

申请日：1991-03-27

申请人： Lajos Gazsi

发明人： Lajos Gazsi

IPC分类号： H03M1/00 ,  H03H17/02 ,  H04B1/58 ,  H04B3/03 ,  H04L25/22

CPC分类号： H04B1/586

摘要： A two-wire/four-wire converter for coupling a two-wire communications path carrying analog transmission and reception signals to a four-wire communications path having a two-wire transmission path carrying digital transmission signals and a two-wire reception path carrying digital reception signals, includes an analog/digital converter having an input coupled to the two-wire communications path and an output coupled to the two-wire reception path. An adder has one input connected to the two-wire reception path and another input connected to the two-wire transmission path. A digital filter with an adjustable communications function generates a predetermined terminating impedance for the two-wire transmission path. The digital filter has an input connected to the output of the adder and an output. A subtractor has one input connected to the output of the digital filter, another input coupled to the output of the analog/digital converter and an output. A digital/analog converter has an input coupled to the output of the subtractor and an output. A resistor is connected between the output of the digital/analog converter and the input of the analog/digital converter.

摘要翻译： 一种用于将携带模拟传输和接收信号的双线通信路径耦合到具有承载数字传输信号的双线传输路径的四线通信路径和承载数字的两线接收路径的双线/四线转换器 接收信号包括具有耦合到两线通信路径的输入和耦合到两线接收路径的输出的模拟/数字转换器。 加法器具有连接到两线接收路径的一个输入端和连接到双线传输路径的另一输入端。 具有可调节通信功能的数字滤波器为双线传输路径产生预定的终端阻抗。 数字滤波器具有连接到加法器的输出的输入和输出。 减法器具有连接到数字滤波器的输出的一个输入，耦合到模拟/数字转换器的输出的另一输入和输出。 数字/模拟转换器具有耦合到减法器的输出和输出的输入。 数模转换器的输出端和模/数转换器的输入端之间连接一个电阻。